BBUL Substrate Routing With Embedded Die Bridge Interconnects
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Solution Overview
Problem
Current semiconductor devices face challenges with low-density substrate routing, which increases system board area, power loss, complexity, and cost, and results in lower chip-to-chip interconnection density, impacting product size and performance.
Innovation Solution
Incorporating a high-density interconnect element, such as a silicon or glass die interconnect bridge, into a bumpless buildup layer (BBUL) substrate to enable localized high-density routing, reducing the need for first-level interconnects and panel processing, and allowing for increased interconnect density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional substrate routing techniques are used, then the substrate can be manufactured with standard processes, but the routing density is low which increases system board area and reduces interconnection density
Solution Approach 1:
The patent applies local quality by creating high-density interconnect elements at specific locations within the substrate where chips are mounted, while maintaining standard substrate routing in other areas. This localized high-density routing approach allows the substrate to provide chip-to-chip interconnection with density comparable to chip-level routing only at the necessary locations, thereby reducing overall system board area without requiring the entire substrate to be manufactured with high-density processes.
Solution Approach 2:
The patent implements the nested doll principle by embedding high-density interconnect elements within the substrate structure itself. These interconnect elements are nested between the substrate layers and provide additional routing capacity without increasing the external dimensions of the substrate or system board. The high-density interconnects are effectively nested within the existing substrate architecture, allowing increased interconnection density without proportionally increasing board area.
2Manufacturing precision
If high-density interconnect elements are incorporated into the substrate, then chip-to-chip interconnection density is improved, but the device complexity and manufacturing process complexity increase
Solution Approach 1:
The patent applies segmentation by dividing the substrate routing function into two distinct segments: standard substrate routing for general connections and high-density interconnect elements for chip-to-chip connections. This segmentation allows each segment to be optimized independently - the standard routing uses conventional, simpler processes while the high-density interconnects provide enhanced capability only where needed. The segmented approach reduces overall device complexity by maintaining simplicity in the majority of the substrate while adding complexity only in localized high-value areas.
Solution Approach 2:
The patent uses the substrate as an intermediary structure that hosts both standard routing and high-density interconnect elements. The substrate acts as a mediator between the chips and the external board, providing multiple levels of interconnection density appropriate to different functional requirements. This intermediary approach allows the system to achieve high interconnect density without requiring the entire system architecture to be complex, as the substrate intermediates between the simple chip-level interfaces and the external board connections.
3Ease of manufacture
If low-density substrate routing is used, then manufacturing is simpler and cost is reduced, but power loss increases and performance is impacted
Solution Approach 1:
The patent applies local quality by implementing high-density interconnect elements only in the specific regions where chips are mounted and high-speed signals are transmitted. This localized approach concentrates the manufacturing complexity and cost only where it is necessary to reduce power loss and improve performance, while the majority of the substrate can be manufactured with simpler, lower-cost processes. The local quality principle ensures that the trade-off between manufacturing simplicity and power efficiency is optimized at the precise locations where it matters most.
Data Source
AI summary
Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.