BBUL Package Warpage Reduction via Backside Control Structure
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Solution Overview
Problem
Microelectronic device packages experience warpage issues at room and reflow temperatures, leading to potential damage and connection problems during attachment to external devices, due to in-plane compressive stresses on transistors.
Innovation Solution
A bumpless build-up layer (BBUL) coreless microelectronic package design incorporating a warpage control structure with a layered composition of high coefficient of thermal expansion (CTE) material, such as silica-filled epoxy, and high elastic modulus material, like copper, disposed on the back surface of the device to reduce warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional microelectronic device package is used, then the device can be manufactured and assembled, but warpage occurs at room and reflow temperatures causing potential damage and connection problems
Solution Approach 1:
A warpage control structure is formed on the back surface of the microelectronic device before packaging. This structure includes a first layer with high coefficient of thermal expansion and a second layer with high elastic modulus, positioned to counteract the in-plane compressive stresses that cause warpage during subsequent processing and operation, thereby preventing connection reliability issues before they occur
Solution Approach 2:
The warpage control structure utilizes materials with specific thermal expansion parameters - the first layer has a high coefficient of thermal expansion and the second layer has a high elastic modulus. These parameter choices enable the structure to effectively compensate for thermal-induced warpage across different temperature conditions, including room temperature and reflow temperatures
2Productivity
If in-plane compressive stresses are present on transistors, then the device can operate, but warpage and potential device damage occur
Solution Approach 1:
The warpage control structure acts as a counterbalancing element on the back surface of the device. The first layer with high thermal expansion and the second layer with high elastic modulus work together to provide a counteracting force against the in-plane compressive stresses on the transistors, reducing warpage and preventing damage while maintaining device operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The warpage control structure effectively minimizes package warpage at both room and reflow temperatures, reducing the risk of device damage and connection issues, and enhancing the performance of microelectronic devices by alleviating compressive stresses on transistors.
Implementation Method 1
a first layer comprising a high coefficient of thermal expansion material, including but not limited to, a filled epoxy
Implementation Method 2
a second layer comprising a high elastic modulus material, such as, but not limited to, a metal layer
Data Source
AI summary
The present disclosure relates to the field of fabricating microelectronic packages and the fabrication thereof, wherein a microelectronic device may be formed within a bumpless build-up layer coreless (BBUL-C) microelectronic package and wherein a warpage control structure may be disposed on a back surface of the microelectronic device. The warpage control structure may be a layered structure comprising at least one layer of high coefficient of thermal expansion material, including but not limited to a filled epoxy material, and at least one high elastic modulus material layer, such as a metal layer.