BCAT Word Line Trench Formation via Sacrificial Layer Segmentation

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Solution Overview

Problem

As the degree of integration of integrated circuit devices increases, there is a need to improve and stabilize the operation and reliability of buried channel array transistors (BCATs) while maintaining electrical reliability despite a reduction in device area.

Innovation Solution

A method of manufacturing integrated circuit devices involves forming a semiconductor substrate with a buried channel array transistor structure, including sequential layers such as a lower insulation layer, buried layer, and sacrificial layers, where polysilicon is used in the first sacrificial layer, and etch masks are employed to create word line trenches, allowing for precise patterning and area reduction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If the degree of integration is increased to reduce device area, then area is reduced, but electrical reliability deteriorates

Engineering Contradiction:
Improvedevice areaVSAvoidelectrical reliability
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The patent divides the word line formation process into multiple discrete steps using different sacrificial layers (first, second, and third sacrificial layers) with distinct materials and removal sequences. This segmentation allows precise control over the trench formation process, enabling reliable electrical connections even in highly integrated devices with reduced area.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs preliminary actions by forming multiple sacrificial layers before the actual word line trench formation. These sacrificial layers are sequentially removed to create the trench structure, ensuring that the trench is formed with precise dimensions and proper isolation from surrounding structures, thereby maintaining electrical reliability in compact designs.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If multiple sacrificial layers are used to enable precise patterning, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improvepatterning precisionVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent uses sacrificial layers as intermediary materials that facilitate the formation of the word line trench. These intermediaries are temporarily introduced, precisely patterned, and then selectively removed to create the desired trench structure. This approach achieves high manufacturing precision while managing complexity through the systematic use of removable intermediary structures.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent employs multiple sacrificial layers that are sequentially removed after serving their patterning function. Each sacrificial layer is discarded after enabling the formation of the next structural element, allowing complex precise patterning to be achieved through a series of simpler, manageable steps rather than a single complex process.

Inventive Principle:
Principle #34Discarding and recovering

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enhances the integration and reliability of integrated circuit devices by enabling the formation of efficient word line trenches, thereby improving the operational stability and reliability of BCATs within a reduced device area.

Implementation Method 1

removing a portion of the lower insulation layer and a portion of the semiconductor substrate by using the buried pattern as an etch mask to form a word line trench

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS20240071771A1Method of manufacturing integrated circuit device
Publication Date: 2024.02.29 SAMSUNG ELECTRONICS CO LTD
  • US20240071771A1 patent drawing
  • US20240071771A1 patent drawing
  • US20240071771A1 patent drawing

AI summary

A method of manufacturing an integrated circuit device includes preparing a semiconductor substrate having an active area and a field area, sequentially forming a lower insulation layer, a buried layer, a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer on the semiconductor substrate, removing a portion of the third sacrificial layer to form a first sacrificial pattern, removing a portion of the second sacrificial layer and the first sacrificial pattern to form a second sacrificial pattern, removing a portion of the first sacrificial layer and the second sacrificial pattern to form a third sacrificial pattern, removing a portion of the buried layer and the third sacrificial pattern to form a buried pattern, and removing a portion of the lower insulation layer and a portion of the semiconductor substrate by using the buried pattern as an etch mask to form a word line trench.