BCD Process for Compatible LDMOS and VDMOS Transistors
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Solution Overview
Problem
The existing BCD process cannot accommodate both LDMOS and VDMOS transistors on the same platform, limiting the integration of high voltage-resistance and large current driving capability.
Innovation Solution
A method for fabricating an LDMOS transistor compatible with VDMOS by preparing a substrate with separate areas for each, forming specific layers and structures such as N-buried layers, wells, isolation areas, drift areas, gates, PBODY areas, N-type GRADE areas, and NSINK areas, allowing for compatibility and enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the existing BCD process uses LDMOS transistors, then high voltage-resistance is achieved, but large current driving capability cannot be obtained
Solution Approach 1:
The patent divides the transistor structure into two distinct types within the same BCD process: LDMOS transistors for high voltage-resistance applications and VDMOS transistors for large current driving capability applications. This segmentation allows each transistor type to be optimized for its specific function without compromising the other, resolving the contradiction between voltage-resistance and current driving capability.
Solution Approach 2:
The patent creates a universal BCD process platform that can manufacture both LDMOS and VDMOS transistors using the same fabrication steps. The process is designed to be multi-functional, accommodating different transistor architectures (lateral for LDMOS, vertical for VDMOS) through a single integrated manufacturing flow, thereby enabling both high voltage-resistance and large current driving capability from the same process.
2Adaptability or versatility
If the existing BCD process integrates BIPOLAR, CMOS and DMOS, then complex control function is achieved, but compatibility of LDMOS and VDMOS cannot be accomplished
Solution Approach 1:
The patent applies local quality by designing specific process steps that create different structural outcomes in different regions of the wafer. For example, the field oxidation step creates LOCOS isolation structures for LDMOS devices, while the same process conditions allow vertical well formation for VDMOS devices in other regions. This localized structural differentiation enables both LDMOS and VDMOS compatibility within the same BCD process while maintaining complex control functions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the compatibility of LDMOS and VDMOS transistors on a BCD process platform, accommodating high voltage and large current demands.
Implementation Method 1
ions are injected into the substrate to form an N-buried layer area
Implementation Method 2
an epitaxial layer is formed on the N-buried layer area by an epitaxial method
Implementation Method 3
ions are injected into the epitaxial layer to form an N-well and a P-well
Implementation Method 4
an isolation area is formed at the interface between the N-well and the P-well by a field oxidation method
Implementation Method 5
ions are injected into the epitaxial layer in the area of the P-well to form a drift area
Implementation Method 6
a gate is formed on a part of the epitaxial layer and a part of the drift area
Implementation Method 7
ions are injected into the epitaxial layer to form a PBODY area
Implementation Method 8
ions are injected into the epitaxial layer to form an N-type GRADE area
Implementation Method 9
an NSINK area is formed in the epitaxial layer between the isolation area and an adjacent gate, wherein the NSINK area is communicated with the N-buried layer area
Data Source
AI summary
A method for manufacturing compatible vertical double diffused metal oxide semiconductor (VDMOS) transistor and lateral double diffused metal oxide semiconductor (LDMOS) transistor includes: providing a substrate having an LDMOS transistor region and a VDMOS transistor region; forming an N-buried region in the substrate; forming an epitaxial layer on the N-buried layer region; forming isolation regions in the LDMOS transistor region and the VDMOS transistor region; forming a drift region in the LDMOS transistor region; forming gates in the LDMOS transistor region and the VDMOS transistor region; forming PBODY regions in the LDMOS transistor region and the VDMOS transistor region; forming an N-type GRADE region in the LDMOS transistor region; forming an NSINK region in the VDMOS transistor region, where the NSINK region is in contact with the N-buried layer region; forming sources and drains in the LDMOS transistor region and the VDMOS transistor region; and forming a P+ region in the LDMOS transistor region, where the P+ region is in contact with the source.