BCD Semiconductor Device with Lightly-Doped Well for Noise Reduction
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Solution Overview
Problem
Noise is a major performance limiting factor in bipolar CMOS DMOS (BCD) integrated circuit devices, affecting signal integrity and resolution in analog and mixed-signal applications.
Innovation Solution
A low-noise, high-gain semiconductor device is formed using a substrate with specific dopant concentrations and active regions, coupled with a gate structure comprising a doped silicon polycrystalline layer and an oxide layer, which increases majority carrier mobility and reduces intrinsic noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If conventional BCD process devices are used, then integration of bipolar and CMOS technology is achieved, but noise performance deteriorates
Solution Approach 1:
The patent applies local quality by creating a lightly-doped n-type well region with specific dopant concentration (1×10^10 to 1×10^19 atoms/cm³) in a localized area beneath the channel. This localized doping modification reduces thermal noise generation at the critical channel region while maintaining the overall BCD device structure and functionality.
Solution Approach 2:
The patent changes the dopant concentration parameter in the substrate well region to achieve low-noise performance. By setting the n-type well dopant concentration to a specific range (1×10^10 to 1×10^19 atoms/cm³), the device achieves reduced thermal noise while maintaining proper transistor operation and high-gain characteristics.
2Speed
If bipolar devices are used for high-frequency analog amplifiers, then high gain and high speed are achieved, but noise increases
Solution Approach 1:
The patent applies local quality by modifying only the well region doping characteristics beneath the channel, leaving the active regions and gate structure unchanged. This localized modification reduces thermal noise in the channel region while preserving the high-frequency speed characteristics of the bipolar device.
Solution Approach 2:
The patent creates a composite doping structure with a lightly-doped n-type well region combined with heavily-doped p-type active regions. This composite structure enables the device to simultaneously achieve high-frequency response from the bipolar junction and low noise from the lightly-doped channel region.
3Use of energy by moving object
If CMOS technology is used, then high input resistance and low-power logic gates are achieved, but transconductance factor is limited
Solution Approach 1:
The patent changes the substrate well dopant concentration parameter to a lightly-doped state (1×10^10 to 1×10^19 atoms/cm³), which increases carrier mobility in the channel. This parameter change increases the transconductance factor while the device maintains the low-power operation characteristics of CMOS technology.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves up to 80% increase in transconductance factor and 50% reduction in intrinsic noise compared to similar devices, improving device matching and signal quality.
Implementation Method 1
increases majority carrier mobility and reduces intrinsic noise
Implementation Method 2
the arrow illustrates a buried conduction channel due to the work function of the gate structure
Data Source
AI summary
Techniques are described to form a low-noise, high-gain semiconductor device. In one or more implementations, the device includes a substrate including a first dopant material having a concentration ranging from about 1×1010/cm3 to about 1×1019/cm3. The substrate also includes at least two active regions formed proximate to a surface of the substrate. The at least two active regions include a second dopant material, which is different than the first dopant material. The device further includes a gate structure formed over the surface of the substrate between the active regions. The gate structure includes a doped polycrystalline layer and an oxide layer formed over the surface between the surface and the doped polycrystalline layer. The doped polycrystalline layer includes the first dopant material having a concentration ranging from about 1×1019/cm3 to about 1×1021/cm3.