BCE IGZO TFT Device Manufacturing Method
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Solution Overview
Problem
In the manufacturing of BCE IGZO TFT devices, the use of a gate insulating layer mask during the bonding of metal layers leads to difficulties in etching the IGZO material, resulting in abnormal overlap of electrode layers and quality issues due to the production of IGZO tails during the dry etching process.
Innovation Solution
A manufacturing method for BCE IGZO TFT devices that involves depositing a first metal layer to form a gate and electrode layer, followed by a gate insulating layer, and then an active IGZO layer in direct contact, with a second metal layer forming source, drain, and electrode layers without an etching process, using a substrate with a multilayer film structure of silicon nitride, silicon oxide, or aluminum oxide, and metal layers like Cu, Al, or Mo.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a gate insulating layer mask is added to facilitate bonding of metal layers, then the bonding process is improved, but IGZO tail is produced during dry etching, causing abnormal overlap of electrode layers
Solution Approach 1:
The patent removes the gate insulating layer mask from the manufacturing process. By extracting this unnecessary component, the process eliminates the root cause of IGZO tail formation while maintaining proper electrode layer alignment through direct patterning methods
Solution Approach 2:
Instead of using a mask to enable bonding (conventional approach), the patent inverts the approach by removing the mask entirely and achieving bonding through direct metal layer deposition and patterning, thereby avoiding the harmful side effects of mask usage
2Ease of manufacture
If dry etching process is used on gate insulating layer with mask, then metal layer bonding is facilitated, but IGZO material cannot be etched properly, producing IGZO tails
Solution Approach 1:
The patent converts the harmful interaction between dry etching and IGZO material into a beneficial process by eliminating the etching step entirely. The direct patterning approach transforms what was previously a harmful process (etching that creates tails) into a clean deposition process that avoids IGZO contamination
Solution Approach 2:
The patent introduces a new intermediary process (direct metal deposition and patterning) that mediates between the need for metal layer bonding and the avoidance of IGZO tail formation, replacing the problematic mask-etching sequence with a cleaner alternative
3Ease of manufacture
If gate insulating layer mask is used, then first and second metal layer bonding is enabled, but electrode layer quality deteriorates due to abnormal overlap
Solution Approach 1:
The patent extracts the gate insulating layer mask from the process, eliminating the source of alignment errors that cause abnormal electrode layer overlap and subsequent quality deterioration
Solution Approach 2:
The patent performs preliminary patterning of metal layers with precise alignment before subsequent processing steps, ensuring that electrode layers are correctly positioned from the outset, preventing abnormal overlap and maintaining high reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method prevents IGZO tail formation, improves the transfer between electrode layers, enhances product yield, and reduces production costs by eliminating the need for etching processes.
Implementation Method 1
depositing a first metal layer on the substrate, and the first metal layer forming a gate and a first electrode layer by a patterning process
Implementation Method 2
depositing a gate insulating layer on the substrate, the gate, and the first electrode layer
Implementation Method 3
IGZO cannot be etched in the dry etching process of the gate insulating layer
Implementation Method 4
IGZO materials are susceptible to hydrogen doping, producing lots of charge carrier and then becoming conductors
Data Source
AI summary
A BCE IGZO TFT device and a manufacturing method thereof include steps of providing a substrate, depositing a first metal layer on the substrate, wherein the first metal layer forms a gate and a first electrode layer by a patterning process, depositing a gate insulating layer on the substrate, the gate, and the first electrode layer, wherein the gate insulating layer is etched to remove a part of the gate insulating layer on a surface of the first electrode layer, depositing an active layer on the first electrode layer and the gate insulating layer, wherein the active layer and the first electrode layer are in direct contact, and depositing a second metal layer on the active layer, wherein the second metal layer forms a source, a drain, and a second electrode layer by a patterning process.