BCE TFT Insulating Layer Layout for Lower Vgs and Capacitance
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Solution Overview
Problem
Conventional back-channel etched (BCE) thin-film transistors (TFTs) face a trade-off between reducing the thickness of the gate insulating layer to improve electrical performance, which decreases pressure resistance and increases capacitance between the gate and source/drain, affecting overall electrical performance.
Innovation Solution
The proposed solution involves a TFT structure with a gate insulating layer and an interlayer insulating layer, where the interlayer insulating layer is thicker than the gate insulating layer, allowing for independent adjustment of their thicknesses to reduce Vgs and enhance pressure resistance and capacitance, while the gate and first electrode are disposed on opposite sides of the active layer, enabling individual optimization of insulating layers to improve comprehensive electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the thickness of the gate insulating layer is reduced to improve electrical performance, then Vgs is reduced, but pressure resistance between gate and drain decreases and capacitance between gate and source/drain increases
Solution Approach 1:
The patent divides the insulating structure into two separate layers: a gate insulating layer between the gate and active layer, and an interlayer insulating layer between the drain electrode and active layer. This segmentation allows independent optimization of each layer's thickness - the gate insulating layer can be made thin to reduce Vgs, while the interlayer insulating layer can be made thick to maintain pressure resistance and control capacitance, thereby resolving the technical contradiction.
2Use of energy by moving object
If the thickness of the gate insulating layer is reduced to improve electrical performance, then Vgs is reduced, but capacitance between gate and source/drain increases
Solution Approach 1:
By segmenting the insulating structure into gate insulating layer and interlayer insulating layer, the patent enables independent thickness optimization. The gate insulating layer thickness is reduced to lower Vgs, while the interlayer insulating layer thickness is increased to reduce capacitance between the drain electrode and active layer, thus resolving the contradiction between reducing Vgs and controlling capacitance.
Solution Approach 2:
The patent applies different thickness specifications to different regions of the insulating structure. The gate insulating layer has a smaller thickness (50-150 nm) optimized for electrical performance, while the interlayer insulating layer has a larger thickness (150-300 nm) optimized for capacitance control. This local differentiation of quality resolves the technical contradiction by optimizing each region for its specific function.
Data Source
AI summary
A thin-film transistor (TFT), a display panel, and a manufacturing method of the display panel are provided. The TFT includes: a gate, a gate insulating layer, an active layer, a first electrode, an interlayer insulating layer, and a second electrode. The interlayer insulating layer is disposed between the first electrode and the active layer. A first via is defined on the interlayer insulating layer. The active layer is connected to the first electrode by the first via. A thickness of the interlayer insulating layer is greater than a thickness of the gate insulating layer. The second electrode is connected to the active layer.