BCH Decoder Clock Scaling Based on Error Count
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Solution Overview
Problem
Current error correction decoding methods in communications systems, such as those using BCH codes, consume significant power due to the complexity of calculations, particularly in determining error locations and correcting errors in digital information transmitted over noisy channels.
Innovation Solution
A method and apparatus that adjust the frequency of a clock signal provided to search algorithm hardware, like the Chien search algorithm, based on the error count derived from the highest order term of the error location polynomial, reducing power consumption by either stepping down the frequency when it's higher than a reference or maintaining it when equal to or lower than the reference, and resetting it to an initial value after corrections are made.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If error correction decoding is performed using traditional fixed-frequency clock signals, then decoding accuracy is maintained, but power consumption increases due to constant high-frequency operation regardless of error count
Solution Approach 1:
The patent applies dynamics by making the clock signal frequency variable rather than fixed. The frequency adjustment logic dynamically changes the clock frequency based on the error count from the highest order term of the error location polynomial. When error count is low, frequency is reduced to save power; when error count is high, frequency is maintained or increased to ensure decoding speed, thus resolving the contradiction between power consumption and decoding productivity
Solution Approach 2:
The patent changes the parameter of clock signal frequency based on the error count parameter. The frequency adjustment logic monitors the error count and adjusts the clock frequency accordingly, transforming the static frequency parameter into a dynamic one that adapts to the actual decoding needs, thereby reducing power consumption without significantly impacting decoding productivity when errors are few
2Use of energy by moving object
If clock signal frequency is reduced to lower power consumption, then energy usage decreases, but decoding speed and processing capability are compromised
Solution Approach 1:
The system dynamically adjusts clock frequency based on real-time error count assessment. The frequency adjustment logic ensures that frequency is only reduced when the error count indicates low complexity, maintaining processing speed when needed while saving energy when possible, thus dynamically balancing power consumption and processing speed
Solution Approach 2:
The patent implements feedback by using the error count (derived from the highest order term of the error location polynomial) as feedback signal to control the clock frequency. The frequency adjustment logic continuously monitors the error count and adjusts frequency accordingly, creating a closed-loop control system that adapts processing speed to actual workload, reducing power consumption without permanently compromising processing capability
3Productivity
If high clock frequency is maintained to ensure decoding speed, then processing capability is preserved, but power consumption increases unnecessarily when error count is low
Solution Approach 1:
The patent changes the clock frequency parameter based on the error count parameter. When the highest order term indicates low error count, the frequency adjustment logic reduces the clock frequency, thereby reducing power consumption. When error count is high, the frequency is maintained at higher levels to preserve decoding speed, thus adapting processing parameters to actual needs
Data Source
AI summary
A decoder, a method of decoding and systems implementing the same are disclosed. In one example, the method includes calculating syndrome values from input codewords, generating an error location polynomial about the codewords using the syndrome values, determining an error count in the codewords using the error location polynomial, and adjusting power consumption of a circuit in response to the determined error count in the codewords. In one example, a frequency of a clock signal to be provided to a search circuit may be determined based on the error count, and the clock signal may be provided having the determined frequency to a search circuit, such as a Chien search circuit.