BCH Decoder Architecture for High-Throughput Flash Error Correction
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Solution Overview
Problem
BCH decoder designs in flash memory controllers face challenges in achieving high throughput while managing limited hardware resources, particularly due to the computational expense of the Berlekamp-Massey Algorithm (BMA) and the need for Galois field inversion operations.
Innovation Solution
The implementation of Inversionless BMA, Scalable Semi-Parallel Shared BMA Multiplier Architecture, and Conditional q-ary/Binary Inversionless BMA operations, which reduce the gate count and power consumption by eliminating division operations and optimizing multiplier architectures, allowing for higher throughput with fewer multipliers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional BMA with Galois field inversion operations is used, then decoding accuracy is maintained, but hardware resource consumption and power usage increase
Solution Approach 1:
The patent extracts and removes the Galois field inversion operation from the BMA implementation. By eliminating this computationally expensive operation, the patent reduces hardware resource requirements while maintaining the core error correction functionality through alternative computational approaches.
Solution Approach 2:
The patent changes the computational parameters of the BMA by using modified algorithms that avoid inversion operations. This involves transforming the mathematical approach from one requiring field inversion to one using only multiplication and addition operations, thereby reducing hardware complexity.
2Productivity
If traditional BMA with full parallel multiplier architecture is used, then decoding throughput is improved, but power consumption and gate count increase
Solution Approach 1:
The patent introduces dynamic scaling of the multiplier architecture, allowing the system to adapt the number of parallel multipliers based on the actual error correction needs. This dynamic approach enables high throughput when necessary while reducing power consumption during normal operation with fewer errors.
Solution Approach 2:
The patent implements a scalable multiplier architecture that uses partial parallelism rather than full parallelism. By deploying only the necessary number of multipliers based on error patterns, the system achieves adequate throughput without the excessive power consumption of a fully parallel implementation.
3Reliability
If higher correction strength BCH decoding is implemented, then error correction capability is improved, but hardware resource requirements increase
Solution Approach 1:
The patent segments the BCH decoding process into modular components that can be selectively activated. This segmentation allows the system to implement higher correction strength by enabling specific correction modules while keeping the overall hardware footprint manageable through shared resources.
Solution Approach 2:
The patent designs universal hardware components that can handle multiple correction strengths. The same multiplier architecture and processing units can be configured for different BCH code rates and correction capabilities, eliminating the need for separate hardware implementations for each correction level.
Data Source
AI summary
Methods and apparatuses for Bose-Chaudhuri-Hocquenghem (BCH) decoding utilizing Berlekamp-Massey Algorithm (BMA) and Chien Search. The BMA may utilize one or more of a scalable semi-parallel shared multiplier array, a conditional q-ary inversionless BMA and/or a conditional binary Inversionless BMA. The Chien Search may be accomplished utilizing a non-rectangular multiplier array.