BCH Decoder Logic Simplification for FPGA Area Efficiency
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Solution Overview
Problem
Conventional BCH decoders implemented in FPGAs require a large number of look-up tables (LUTs), leading to increased power consumption, area occupation, and complex interconnect routing due to the brute force method used for error correction, which is inefficient for field programmable gate arrays.
Innovation Solution
The implementation of a BCH decoder in an FPGA using an electronic design automation (EDA) tool that simplifies logic by arranging expressions in a binary matrix, forming submatrices, determining subexpressions, and mapping them into LUT clusters, reducing the number of LUTs required and optimizing power consumption and area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional parallel Chien search circuit is implemented in FPGA using brute force method, then error correction functionality is achieved, but the number of LUTs increases significantly leading to high power consumption and large area occupation
Solution Approach 1:
The patent segments the error correction process into distinct modules: syndrome calculation unit, error locator polynomial generation unit, and Chien search unit. This segmentation allows each module to be optimized independently for power efficiency while maintaining the complete error correction functionality, thereby resolving the contradiction between reliability and power consumption
Solution Approach 2:
The patent changes the operational parameters of the Chien search circuit by implementing a streamlined version that processes field elements more efficiently. By optimizing the search algorithm's parameter handling and reducing redundant calculations, the design achieves the same error correction reliability with significantly lower power consumption in the FPGA implementation
2Reliability
If a conventional parallel Chien search circuit is implemented in FPGA using brute force method, then error correction functionality is achieved, but area occupation and interconnect routing complexity increase
Solution Approach 1:
By dividing the decoder into segmented functional units with well-defined interfaces, the patent reduces interconnect routing complexity. Each segment processes specific aspects of error correction independently, minimizing the need for complex long-distance interconnections and reducing overall device complexity while preserving error correction capability
Solution Approach 2:
The patent implements universal computational units that can handle multiple operations within the error correction process. The feedback circuit and substitution circuit are designed to perform multiple functions using the same hardware resources, thereby reducing the overall number of components and simplifying interconnect routing while maintaining comprehensive error correction functionality
Data Source
AI summary
A decoder is implemented in a field programmable gate array (FPGA) by performing logic simplification of binary expressions associated with the decoder. To perform the logic simplification, the binary expressions are arranged in a binary matrix. Further, a set of submatrices is formed based on the binary expressions such that rows of each submatrix have common data bits in one or more columns of each submatrix. Based on the common data bits, a set of subexpressions for each submatrix is formed. The set of subexpressions of each submatrix is mapped into look-up table clusters of the FPGA, thereby implementing the decoder in the FPGA.