BCH Decoder Architecture for Low-Power NAND Flash Error Correction
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Solution Overview
Problem
Current error correction methods in NAND flash memory systems, such as Reed-Solomon and Low Density Parity Check codes, face challenges in efficiently decoding data due to high power consumption and complex iterative processes, particularly in handling errors in multilevel algebraic codes like Super Bose-Chaudhuri-Hocquenghem (SBCH) codes.
Innovation Solution
A decoding circuit and method utilizing a Bose-Chaudhuri-Hocquenghem (BCH) decoder with a Syndrome stage, Berlekamp-Massey algorithm, Chien search using Fast Fourier Transform (FFT), and Frame Fixer to reorder error bits, enabling efficient decoding of BCH encoded words with reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Reed-Solomon or LDPC error correction codes are used in NAND flash memory systems, then error detection and correction capability is improved, but power consumption increases and decoding complexity increases
Solution Approach 1:
The patent transforms the error correction approach by changing from iterative probabilistic decoding (LDPC) to algebraic deterministic decoding (BCH). This parameter change in decoding methodology reduces power consumption while maintaining error correction capability through closed-form mathematical solutions instead of iterative processes.
Solution Approach 2:
The patent replaces the mechanical iterative decoding process of LDPC codes with an algebraic mathematical system. By using Berlekamp-Massey algorithm and Forney algorithm for syndrome computation and error correction, the system eliminates the need for repeated iterative operations, thereby reducing power consumption.
2Reliability
If Reed-Solomon or LDPC error correction codes are used in NAND flash memory systems, then error detection and correction capability is improved, but decoding complexity increases
Solution Approach 1:
The patent changes the decoding parameter from iterative probabilistic methods to algebraic deterministic methods. This transformation simplifies the decoding process by using closed-form mathematical solutions through syndrome computation and polynomial-based error location, reducing decoding complexity while maintaining reliability.
Solution Approach 2:
The patent extracts and separates the error correction function into distinct algebraic stages: syndrome computation using Berlekamp-Massey algorithm, error location using Forney algorithm, and error correction. This extraction of the error correction mechanism into modular algebraic components simplifies the overall decoding complexity.
3Reliability
If iterative decoding processes are used for error correction, then error correction capability is improved, but processing time increases
Solution Approach 1:
The patent skips the iterative process entirely by using direct algebraic methods. The Berlekamp-Massey algorithm and Forney algorithm compute error locations and corrections in closed form, allowing the system to rush through the decoding process without repeated iterations, thereby reducing processing time while maintaining error correction capability.
Solution Approach 2:
The patent performs preliminary syndrome computation using algebraic methods that prepare all necessary information for error correction in advance. By computing syndromes and error locations through polynomial operations before actual correction, the system eliminates the need for iterative refinement, reducing processing time.
Data Source
AI summary
A decoding circuit includes a Bose-Chaudhuri-Hocquenghem (BCH) decoder. The BCH decoder includes a Syndrome stage for generating syndromes based on a BCH encoded word, a Berlekamp-Massey (BM) stage performing a Berlekamp-Massey algorithm on the syndromes to generate Error Location Polynomial (ELP) coefficients, a Chien stage that performs a Chien search on the ELP coefficients using a Fast Fourier Transform (FFT) to generate error bits and iteration information, and a Frame Fixer stage configured to reorder the error bits to be sequential based on the iteration information. The BCH decoder decodes the BCH encoded word using the reordered error bits.