BCH Decoder Architecture Using PGZ and BM for Higher Throughput
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Solution Overview
Problem
Current BCH decoder architectures face throughput limitations in decoding encoded data, particularly in scenarios with high bit error rates or limited hardware resources, leading to increased costs and power consumption.
Innovation Solution
Implementing a parallel architecture with multiple engines, such as the Peterson-Gorenstein-Zierler (PGZ) and Berlekamp-Massey Algorithms, to compute the error locator polynomial, where less computationally complex engines handle fewer errors and more complex engines handle higher error corrections, optimizing gate count and throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single BCH decoding algorithm is used, then the gate count is reduced, but the decoding throughput is limited
Solution Approach 1:
The BCH decoding process is segmented into multiple parallel algorithmic engines (e.g., Berlekamp-Massey, Peterson-Gorenstein-Zierler, Euclidean algorithm engines), each capable of independently computing the error locator polynomial. This segmentation enables concurrent processing of different codewords or error patterns, thereby increasing overall decoding throughput without requiring a single overly complex engine that would demand excessive gate count.
Solution Approach 2:
The system dynamically selects which algorithmic engine processes a given codeword based on the number of errors detected in that codeword. Less complex engines (e.g., PGZ) handle codewords with fewer errors, while more complex engines (e.g., BM) handle codewords with higher error rates. This dynamic allocation optimizes resource utilization and throughput while managing gate count effectively.
2Productivity
If multiple algorithm engines are used in parallel, then decoding throughput increases, but hardware resources are consumed
Solution Approach 1:
Different algorithmic engines are assigned different levels of computational complexity matched to the specific error correction needs. Simpler engines like PGZ use fewer hardware resources for low-error scenarios, while more capable engines like BM are reserved for high-error scenarios. This local quality differentiation ensures that hardware resources are not over-provisioned for all cases, optimizing the balance between throughput and resource consumption.
3Reliability
If more complex algorithms are used for high error correction, then error correction capability increases, but power consumption increases
Solution Approach 1:
The system dynamically adjusts the computational complexity of the active decoding engine based on the detected error rate. When error rates are low, simpler and more power-efficient engines (e.g., PGZ) are activated. When error rates exceed certain thresholds, more complex but necessary engines (e.g., BM) are activated. This dynamic adaptation ensures that power consumption is minimized while maintaining adequate error correction capability for the actual channel conditions.
Data Source
AI summary
Bose-Chaudhuri-Hocquenghem (BCH) decoder architectures which execute a plurality of different algorithms to calculate an error location polynomial. The multiple algorithms may be implemented in a storage controller for increased throughput per gate count. Codewords needing up to a threshold number of corrections may be processed via a first algorithm while those with a greater number of corrections may be processed via the second algorithm. In embodiments, the Peterson-Gorenstein-Zierler (PGZ) algorithm and the Berlekamp-Massey algorithm (BMA) are executed either serially or in parallel to increase throughput of the decoder.