BCH Decoder Root Finding Without Chien Search Latency
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Solution Overview
Problem
Existing memory systems, particularly NAND flash memories, face reliability issues due to increased hardware complexity and power consumption from massive parallel architectures required for error correction in codes like TPC and BCH codes, which utilize Chien searches for decoding.
Innovation Solution
A decoder architecture that directly finds the roots of an error location polynomial in one cycle for two-error-correcting BCH codes, using a key equation solver and simplifying hardware computations, avoids Chien searches to improve latency and throughput, and reduces silicon area by integrating a logic for generating error-location polynomials and determining error locations efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Chien searches are used for decoding in massive parallel architectures, then error correction capability is improved, but hardware complexity and power consumption increase
Solution Approach 1:
The patent extracts and eliminates the Chien search component from the decoding architecture. Instead of performing iterative Chien searches to find error locations, the invention directly computes error locations using a simplified polynomial root-finding approach based on syndromes, thereby removing the complex iterative search hardware while maintaining error correction capability
Solution Approach 2:
The patent changes the fundamental parameter of the decoding approach by transitioning from iterative search methods to direct computation methods. By reformulating the error location determination as a direct polynomial evaluation problem rather than a search problem, the hardware complexity is reduced while preserving the ability to correct errors
2Reliability
If Chien searches are used for decoding in massive parallel architectures, then error correction capability is improved, but power consumption increases
Solution Approach 1:
The patent removes the power-intensive Chien search operation from the decoding process. By replacing it with direct polynomial root computation using syndromes, the energy consumption is significantly reduced while maintaining the same error correction functionality
Solution Approach 2:
The patent performs preliminary computation of syndromes and directly uses them to determine error locations without requiring iterative searching. This preliminary preparation of syndrome values enables direct error location calculation, eliminating the need for repeated computational operations that consume power
3Reliability
If Chien searches are used for decoding, then error correction is achieved, but decoding latency increases
Solution Approach 1:
The patent skips the iterative Chien search process entirely and rushes directly to error location determination through polynomial evaluation. By eliminating the step-by-step search iterations, the decoding latency is reduced while still achieving complete error correction
Solution Approach 2:
The patent prepares syndrome values in advance and uses them directly for error location determination without requiring iterative searching. This preliminary computation approach enables single-cycle or low-latency error correction by avoiding time-consuming search iterations
4Productivity
If massive parallel architectures are used for error correction, then throughput is improved, but hardware complexity increases
Solution Approach 1:
The patent extracts the complex iterative search logic from the parallel architecture and replaces it with simple parallel polynomial evaluations. This allows maintaining high throughput through parallelism while eliminating the complexity associated with coordinated iterative searches across multiple processing units
Solution Approach 2:
The patent creates a universal decoding approach that can be implemented with simple parallel hardware units. Each unit independently evaluates polynomial roots using syndrome inputs, providing a multi-functional solution that handles error correction without requiring complex inter-unit coordination or control logic
Data Source
AI summary
A decoder includes a syndrome generator for receiving a codeword and generating at least two syndromes based on the codeword, an error location polynomial generator for generating an error-location polynomial based on the syndromes, an error location determiner for determining at least one error location based on the error-location polynomial, and an error corrector for correcting the codeword based on the one error location. The error location polynomial generator includes a logic for receiving the syndromes and generating a combination of the syndromes as a combination of coefficients of the error-location polynomial, and a key equation solver for generating the error-location polynomial based on the combination of the coefficients and finding at least one root of the error-location polynomial. The error location determiner determines the error location based on a combination of the root and one of the syndromes.