BCH Hardware Decoding Circuit for Fast Memory Bit Error Correction
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Solution Overview
Problem
Existing integrated circuits for security-relevant applications, such as chip card modules and automotive control processors, face challenges in efficiently identifying and correcting bit errors in non-volatile memory with minimal chip area, power consumption, and quick error correction, especially for 1- and 2-bit errors, while maintaining low redundancy and high processing speed.
Innovation Solution
An integrated circuit with a hardware decoding circuit that includes a calculation unit for calculating the syndrome of a message word using a BCH code, a logarithmization unit for establishing logarithms of syndrome components, an arithmetic circuit for determining zeros of the error locator polynomial, and a bit inverter circuit to correct errors, optimizing chip area and power usage by employing precalculated tables and efficient arithmetic operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a hardware decoding circuit is implemented for error correction in non-volatile memory, then error identification and correction capability is improved, but chip area increases
Solution Approach 1:
The decoding circuit is segmented into specialized functional units: syndrome calculation unit, error location determination unit, and error correction unit. Each unit handles a specific aspect of the decoding process, allowing for optimized resource allocation and reduced overall circuit area while maintaining comprehensive error correction capability.
Solution Approach 2:
The circuit implements BCH decoding capability that can correct up to t errors, but in practice focuses on efficiently handling the most common case of 1-2 bit errors. The syndrome calculation and error location determination are optimized for these partial cases, providing sufficient error correction capability without the full overhead of handling maximum theoretical error scenarios.
2Measurement precision
If complex arithmetic operations are performed for BCH decoding, then error correction accuracy is improved, but power consumption increases
Solution Approach 1:
The syndrome calculation is performed immediately upon reading data from non-volatile memory, before any complex error location determination is needed. This preliminary syndrome calculation identifies potential errors early, allowing the system to proceed with error correction only when necessary, thereby reducing overall power consumption while maintaining detection accuracy.
Solution Approach 2:
Complex field arithmetic operations in the Galois Field GF(2^m) are replaced with pre-computed lookup tables and simplified logic operations. The syndrome calculation uses XOR operations instead of full polynomial multiplication, and error location is determined through logarithmic transformations that convert complex arithmetic into simpler bitwise operations, significantly reducing power consumption.
3Reliability
If comprehensive error correction processing is performed, then data integrity is improved, but processing time increases
Solution Approach 1:
The syndrome calculation unit computes error syndromes immediately during the memory read operation, parallel to data retrieval. This preliminary action allows the system to identify errors without delaying the main data read path, and only activates full error correction processing when syndromes indicate actual errors are present, thereby maintaining data integrity while minimizing processing time overhead.
Solution Approach 2:
The circuit implements a fast error location determination mechanism that uses pre-computed logarithmic tables to rapidly identify error positions. When syndromes indicate errors, the system rushes through the error correction process using optimized lookup operations rather than performing exhaustive polynomial root finding, significantly reducing the time penalty for comprehensive error correction while maintaining complete error detection and correction capability.
Data Source
AI summary
An integrated circuit includes a receiver configured to receive a message word and an integrated hardware decoding circuit. The decoding circuit includes a calculation unit to calculate a syndrome of the message word according to a predetermined BCH code, a logarithmization unit to establish a logarithm of each of one or more syndrome components, an arithmetic circuit to establish a logarithm of each of one or more zeros of the error locator polynomial of the BCH code on the basis of the logarithms of the syndrome components, and a bit inverter circuit to invert the one or more bits of the message word, the positions of which are specified by the logarithms of the zeros of the error locator polynomial. The integrated circuit further includes a data processing circuit to process further the message word processed by the bit inverter circuit.