BCH Codeword Decoding with Parallel Bit Correction Logic
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing BCH decoding techniques for correcting multiple bit errors in a codeword are inefficient due to high latency and large area overhead, particularly when computing the roots of the error locator polynomial.
Innovation Solution
The proposed solution involves generating polynomial coefficients for the locator polynomial using syndrome values and simultaneously inputting these coefficients to bit correction logic instances for each bit in the codeword, allowing for parallel decoding and correction of all bits in a single clock cycle, thereby reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple iterations are used to calculate coefficients and find roots of the error locator polynomial, then accurate error correction is achieved, but decoding latency increases
Solution Approach 1:
The patent pre-calculates and stores syndrome values in lookup tables before decoding operations. When decoding is needed, these pre-computed syndrome values are immediately retrieved and used to directly determine error locations without performing iterative calculations during the actual decoding process, thus reducing latency while maintaining accuracy
Solution Approach 2:
The patent creates simplified copies of the error correction logic through lookup tables that store pre-computed relationships between syndromes and error locations. Instead of executing complex iterative algorithms, the system uses these tabulated copies to directly map syndromes to error patterns, achieving fast decoding with reduced computational iterations
2Productivity
If a syndrome look-up table is used to determine error locations, then decoding speed improves, but area overhead increases
Solution Approach 1:
The patent divides the error correction problem into separate segments: syndrome calculation is separated from error location determination. Lookup tables are created only for syndrome-to-error-location mapping, while other parts of the decoding process use different methods. This segmentation reduces the size of individual lookup tables compared to a complete syndrome-to-correction lookup
Solution Approach 2:
The patent transitions from a direct one-dimensional lookup approach to a multi-dimensional decoding structure where syndromes are processed through multiple stages. Instead of a single large lookup table containing all possible error corrections, the system uses multiple smaller tables organized in a hierarchical or staged manner, reducing the area required for storage while maintaining decoding capability
3Reliability
If traditional iterative algorithms are used to solve the error locator polynomial, then comprehensive error correction is achieved, but device complexity increases
Solution Approach 1:
The patent extracts the most computationally intensive part of the iterative algorithm (the coefficient calculations and root-finding iterations) and replaces it with pre-computed lookup tables. This extraction removes the complex iterative logic from the active decoding path, significantly reducing device complexity while preserving the ability to correct multiple errors through the stored lookup data
Data Source
AI summary
Provided are an apparatus, memory device, and method to determine error location polynomial coefficients to provide to bit correction logic instances to decode bits of a codeword. A memory controller for a memory includes coefficient generating logic to receive as input a plurality of syndrome values to generate a plurality of coefficients for an error locator polynomial. A plurality of instances of bit correction logic, one instance for each bit of bits to correct in a codeword for a block in the memory array to decode. Each instance of bit correction logic is to receive as input the coefficients for the error locator polynomial and elements for the bit to correct from a decoder alphabet to determine whether to correct the bit and output as a decoded bit the bit or a corrected bit to include in a decoded codeword.