BCH Error-Correcting Code for Fast NAND Flash Read Correction
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Solution Overview
Problem
As memory cells in nonvolatile memory technologies like NAND Flash and Phase Change Memories become smaller, they become more prone to errors due to factors such as storage charge loss and cosmic rays, making error correction challenging, especially in multi-level architecture where read margins decrease and error probability increases.
Innovation Solution
Implementing a parallel encoding and decoding error correction code (ECC) process based on a 2-bit error correcting binary Bose-Chaudhuri-Hocquenghem (BCH) code, which supplements user data with parity bits and uses specific polynomial operations to minimize latency and area occupancy in memory devices, allowing for reliable correction of up to two errors within tight time constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are made smaller to increase density, then storage capacity is improved, but error probability increases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing syndrome lookup tables before actual error correction is needed. The syndrome values for all possible error patterns are computed in advance and stored in a lookup table, allowing rapid error correction without complex real-time calculations. This resolves the contradiction by enabling fast error correction (improving reliability) with minimal latency penalty.
Solution Approach 2:
The patent uses copying by creating a lookup table that contains pre-computed syndrome values and corresponding error patterns. Instead of performing complex decoding calculations on the actual data, the system copies the pre-stored syndrome information and uses it to quickly identify and correct errors. This approach maintains high reliability while reducing the time and computational resources needed for error correction.
2Reliability
If complex error correction codes are implemented to correct more errors, then reliability is improved, but latency increases
Solution Approach 1:
The patent pre-computes and stores syndrome values for all possible error patterns in lookup tables before runtime. During actual error correction, the system simply queries the lookup table with the computed syndrome, avoiding complex real-time decoding calculations. This enables sophisticated error correction (correcting multiple errors) while maintaining low latency because the heavy computational work was done in advance.
Solution Approach 2:
The patent segments the error correction process into distinct stages: syndrome computation, lookup table querying, and error pattern identification. By dividing the complex decoding process into these manageable segments and using lookup tables for the most computationally intensive parts, the system achieves both high error correction capability and low latency.
3Reliability
If traditional ECC decoding methods are used, then error correction is achieved, but area occupancy increases
Solution Approach 1:
The patent uses copying by storing pre-computed syndrome information in lookup tables that can be implemented using compact memory structures. This replaces the need for large arrays of logic gates and complex decoding circuits with much smaller memory-based storage, significantly reducing the silicon area required for error correction functionality while maintaining full error correction capability.
Data Source
AI summary
Subject matter, for example, disclosed herein relates to an embodiment of a process, system, device, or article involving error correction codes. In a particular embodiment, an error-correcting device may comprise an input port to receive an error correcting code (ECC) based, at least in part, on contents of a memory array; a nonlinear computing block to process the ECC to provide a plurality of signals representing a nonlinear portion of an error locator polynomial; and a linear computing block to process the ECC concurrently with processing the ECC to provide a plurality of signals representing the nonlinear portion of the error locator polynomial, to provide a plurality of signals representing a linear portion of the error locator polynomial.