Variable BCH Error Correction Circuit for NAND Flash Decoding
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Solution Overview
Problem
As memory systems, particularly NAND flash memories, face increasing bit error rates due to the overlap of threshold voltage distributions in multi-level cell programming, existing error correction codes struggle to maintain reliable data integrity without significant changes in system design or operation.
Innovation Solution
The implementation of an error correction circuit using a Bose, Chaudhri, Hocquenghem (BCH) code with varying error correction ability, which generates a codeword comprising a message part, a first parity part, and a second parity part, allowing for error correction decoding using either partial or full codeword values, thereby adapting error correction capability based on the specific requirements of the data being processed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If error correction decoding is performed using partial read values corresponding to a partial codeword including the message part and the first parity part, then decoding speed is improved and power consumption is reduced, but error correction ability is limited compared to using the entire codeword
Solution Approach 1:
The codeword is divided into multiple parts: a message part, a first parity part, and a second parity part. The first parity part contains parity information sufficient for basic error correction, while the second parity part provides additional error correction capability. This segmentation allows the system to perform rapid decoding using only the message part and first parity part when speed is critical, while maintaining the option to use all parts when maximum error correction ability is required.
Solution Approach 2:
The patent implements partial action by allowing error correction decoding to be performed using only a portion of the available parity information (message part + first parity part) rather than requiring the entire codeword. This partial decoding approach achieves acceptable error correction for many cases while significantly reducing decoding time and power consumption, with the option to perform full decoding if needed.
2Reliability
If the entire codeword is used for error correction decoding, then error correction ability is maximized, but decoding time and power consumption increase
Solution Approach 1:
The codeword structure is segmented into a message part, first parity part, and second parity part, where the first parity part is positioned and sized to enable rapid error correction for common error cases. This allows the decoder to achieve high error correction ability for typical scenarios without processing the entire codeword, thus reducing decoding time while maintaining reliability for the majority of cases.
Solution Approach 2:
The system performs partial decoding using only the message part and first parity part for most operations, achieving sufficient error correction ability without the time penalty of processing the entire codeword. Full codeword processing is reserved for cases where maximum error correction is required or when partial decoding fails.
3Reliability
If the entire codeword is used for error correction decoding, then error correction ability is maximized, but power consumption increases
Solution Approach 1:
The error correction code is segmented into multiple parity parts with different computational requirements. The first parity part is designed to provide adequate error correction for common cases with minimal computational effort, while the second parity part provides additional correction capability only when needed. This segmentation significantly reduces power consumption for typical operations while maintaining the option for full error correction when required.
Solution Approach 2:
The system performs partial error correction decoding using only the message part and first parity part for most operations, achieving acceptable error correction ability with substantially reduced power consumption compared to processing the entire codeword. Full decoding is performed only when necessary, optimizing the trade-off between reliability and energy efficiency.
Data Source
AI summary
Provided herein may be an error correction circuit, and a memory controller and a memory system. The error correction circuit may include an encoder configured to generate a codeword comprising a message part, a first parity part, and a second parity part, and a decoder configured to perform error correction decoding using read values corresponding to at least a portion of the codeword, wherein, the decoder is configured to perform error correction decoding based on a first or a second error correction ability such that error correction decoding using the first error correction ability is performed using partial read values corresponding to a partial codeword including the message part and the first parity part, and error correction decoding using the second error correction ability is performed using read values corresponding to the entire codeword, and wherein the second error correction ability is greater than the first error correction ability.