BCH Parity Check Circuit for Faster Flash Memory Error Correction
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Solution Overview
Problem
Conventional flash memory parity check and correction using Reed-Solomon code require long computation time and complex hardware, leading to high manufacturing costs and inefficiencies.
Innovation Solution
An apparatus utilizing Bose-Chaudhuri-Hocquenghem (BCH) code for random parity check and correction, incorporating a BCH encoder and decoder, along with static random access memory (SRAM), to reduce computing time and hardware complexity, employing simplified polynomial equations and XOR gates for encoding and decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Reed-Solomon code is used for parity check and correction in flash memory, then error detection and correction capability is achieved, but computation time is excessively long (4096 cycles)
Solution Approach 1:
The patent changes the code parameters from Reed-Solomon (128, 64) to BCH (128, 64) with specific generator polynomial coefficients. This parameter change reduces the encoding complexity from requiring 4096 cycles to 512 cycles while maintaining the error correction capability for up to 4-bit errors. The BCH code structure with optimized polynomial coefficients enables faster computation.
Solution Approach 2:
The patent segments the parity check and correction process into distinct functional modules: encoding module with simplified polynomial computation, syndrome computation module, error location module, and correction module. This segmentation allows parallel processing and optimizes each module independently, reducing overall computation time from 4096 to 512 cycles.
2Reliability
If Reed-Solomon code encoder and decoder are implemented, then parity check and correction function is provided, but hardware complexity and manufacturing cost increase significantly
Solution Approach 1:
The patent changes from Reed-Solomon code to BCH code with specific parameters (n=128, k=64, t=4) that require fewer hardware resources. The BCH encoder uses a simplified polynomial multiplication structure with fewer multipliers and adders compared to Reed-Solomon, reducing hardware complexity while maintaining error correction capability.
Solution Approach 2:
The patent uses a pre-computed lookup table stored in ROM that contains pre-calculated syndrome values and error correction patterns. Instead of performing complex real-time polynomial computations, the system copies pre-computed values from the lookup table based on the received data, significantly simplifying the hardware architecture and reducing the number of required computational units.
3Reliability
If conventional Reed-Solomon encoding is performed, then data integrity is ensured, but the number of computation stages is excessive
Solution Approach 1:
The patent performs preliminary computation by pre-calculating and storing syndrome values and error correction patterns in a lookup table before actual data encoding. This preliminary action eliminates the need for complex real-time polynomial computations during encoding, reducing the number of computation stages from multiple sequential operations to a single table lookup and XOR operation, thereby increasing encoding speed.
Solution Approach 2:
The patent replaces the mechanical polynomial multiplication and division operations with a lookup table-based system. Instead of physically implementing multiple computation stages for polynomial operations, the system substitutes these with memory access and simple XOR operations, dramatically reducing the number of computation stages and improving productivity.
Data Source
AI summary
An apparatus for random parity check and correction with BCH code is provided, including a Bose-Chaudhuri-Hocquenghem (BCH) parity check code encoder, a channel, a BCH parity check code decoder, and a static random access memory (SRAM). The BCH parity check code encoder uses the BCH encoding to encode the parity check code in writing to flash memory. The channel is connected to the BCH parity check code encoder to compute the parity check code and the message polynomial into receiving data. The BCH parity check code decoder is connected to the channel for inputting the receiving data and using BCH decoding to compute the eigen value and error address. The SRAM is connected to the BCH parity check code decoder so as to read error address from static RAM, correct the data and restores the corrected data to the SRAM. Therefore, this achieves the object of random parity check and correction with BCH code.