Concatenated BCH-LDPC Error Correction for Storage Controllers
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Solution Overview
Problem
Current data storage systems face inefficiencies in error correction, as existing methods consume memory, slow down data storage devices, and require additional circuitry to detect and correct larger data errors effectively.
Innovation Solution
A method employing a concatenated error correction code system using an inner Bose-Chaudhuri-Hocquenghem (BCH) code and an outer Low-Density Parity Check (LDPC) code, where data is initially encoded with BCH and then with LDPC, allowing for efficient error correction with reduced hardware requirements by leveraging LDPC's soft-error correction capabilities only when BCH fails.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If typical error correction techniques are used to detect and correct large errors, then data integrity is improved, but memory consumption increases, device speed decreases, and additional circuitry is required
Solution Approach 1:
The patent divides the error correction task into two segments: BCH code handles common single-bit errors, while LDPC code handles larger error patterns. This segmentation allows each decoder to be optimized for its specific error type, reducing overall system complexity compared to using a single powerful decoder for all error types.
Solution Approach 2:
The patent changes the operational parameters of the error correction system by using BCH code as the primary correction mechanism for typical errors, and only invoking LDPC code when BCH correction fails. This parameter change (conditional deployment based on error detection) reduces average-case complexity while maintaining maximum error correction capability when needed.
2Reliability
If typical error correction techniques are used to detect and correct large errors, then data integrity is improved, but device speed decreases
Solution Approach 1:
The patent applies partial action by using BCH correction for the majority of cases (single-bit errors) and only applying the more computationally intensive LDPC correction when necessary. This partial deployment of full error correction capability maintains data integrity while significantly improving average device speed.
Solution Approach 2:
The two-stage error correction process segments computation based on error severity: fast BCH correction handles typical cases, and slower LDPC correction handles exceptional cases. This segmentation creates a speed advantage for common operations while preserving the ability to correct large errors when they occur.
3Reliability
If typical error correction techniques are used to detect and correct large errors, then data integrity is improved, but memory consumption increases
Solution Approach 1:
The patent segments the error correction functionality into two distinct code types with different memory requirements. BCH code requires less memory and handles common errors, while LDPC code with higher memory requirements is only invoked when necessary. This segmentation reduces average memory consumption while maintaining the capability to correct large errors.
Data Source
AI summary
A method of operating a storage controller is provided. The method includes determining encoded data to be written to a storage media by applying at least an initial encoding comprising a first error correcting code type and a subsequent encoding comprising a second error correcting code type. The method further includes writing the encoded data to the storage media, and responsive to reading the encoded data from the storage media, processing the encoded data into primary decoded data using one or more primary decoders employing the second error correcting code type and detecting when data errors arise in the decoded data. The method also includes based at least on detecting one or more data errors in the decoded data, processing the encoded data into secondary decoded data using one or more secondary decoders employing the first error correcting code type.