BCH Parity-Check Matrix Reordering for Adjacent Error Correction
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Solution Overview
Problem
As technology scales downward, the soft error rate in microprocessor memory systems increases, leading to frequent single-bit and multiple-bit upsets due to particle strikes and noise phenomena, making it challenging to detect and correct adjacent errors effectively.
Innovation Solution
The method involves reordering the columns in the parity-check matrix (H-matrix) of BCH-based error correction codes to map syndromes for adjacent errors to distinct values, enabling exclusive identification and correction of errors without requiring additional ECC check bits, thereby enhancing error coverage and relaxing inter-leaving restrictions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional BCH-based error correction codes are used, then single-bit and double-bit errors can be corrected, but adjacent errors cannot be effectively corrected
Solution Approach 1:
The patent reorders the columns in the parity-check matrix (H-matrix) of BCH-based error correction codes to map syndromes for adjacent errors to distinct values. This parameter change in the H-matrix structure enables the existing ECC check bits to correct adjacent errors without adding more check bits, thereby improving reliability while maintaining the same device complexity.
2Reliability
If additional ECC check bits are added to correct adjacent errors, then error coverage improves, but logic overhead increases
Solution Approach 1:
The patent achieves enhanced error coverage by reordering columns in the H-matrix, which maps adjacent error syndromes to distinct values. This parameter change allows the existing ECC check bits to identify and correct adjacent errors without requiring additional check bits, thus improving error coverage while minimizing logic overhead.
Solution Approach 2:
The reordered H-matrix structure enables the existing ECC check bits to serve multiple functions: correcting single-bit errors, double-bit errors, and adjacent errors. This multi-functionality improves error coverage without requiring additional dedicated check bits for adjacent error correction, thereby reducing logic overhead.
3Productivity
If technology scales downward to improve processing power, then productivity increases, but soft error rate increases
Solution Approach 1:
The patent addresses the increased soft error rate from technology scaling by modifying the H-matrix column order to provide enhanced adjacent error correction capability. This parameter change allows the system to maintain higher productivity from scaled-down technology while compensating for the increased soft error rate through improved error correction.
Data Source
AI summary
An apparatus is provided that comprises a processor. The processor comprises a cache to store data, a decoder, an error classification module, and an error correction module. The cache stores data, the data encoded as a codeword. The decoder reads the codeword from cache and calculates a syndrome of the codeword using an H-matrix. The error classification module determines an error type of the syndrome. The H-matrix is redesigned such that the columns form a geometrical sequence, and as a result not only t-bit random errors but also (t+1) bit adjacent errors can be corrected. The error correction module, triggered by the enhanced error classification module, takes one of two sets of inputs depending on error type (either random error or adjacent error) and produces corrected data from the syndrome when the syndrome comprises a detectable and correctable error.