BCH Syndrome-to-Parity Decoder for Multi-Length Memory ECC
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Solution Overview
Problem
Existing error correcting codes, such as Bose-Chaudhuri-Hocquenghem (BCH) codes, do not efficiently reduce area on a chip through syndrome-to-parity conversion, which is necessary for complex memory devices prone to errors due to factors like storage charge loss and cosmic rays.
Innovation Solution
Implementing a BCH error correcting code that utilizes a syndrome-to-parity conversion to reduce decoder area, allowing for efficient error location and encoding, while preserving a flip property and supporting multiple payload lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If BCH error correcting codes are used for complex memory devices, then error correction capability is improved, but decoder area on chip increases
Solution Approach 1:
The patent combines syndrome computation and parity conversion into a single integrated process. The syndrome-to-parity conversion merges multiple functions (syndrome calculation, error detection, and parity generation) into one unified operation, reducing the overall decoder area while maintaining BCH error correction capability.
Solution Approach 2:
The decoder is designed to handle multiple payload lengths (e.g., 256-bit, 512-bit, 1024-bit payloads) using the same syndrome-to-parity conversion mechanism. This multi-functional approach eliminates the need for separate decoders for different payload sizes, significantly reducing total decoder area while maintaining full error correction capability across all payload lengths.
2Area of stationary object
If syndrome-to-parity conversion is implemented for BCH codes, then decoder area is reduced, but complexity of the conversion process increases
Solution Approach 1:
The syndrome-to-parity conversion process is segmented into distinct computational stages: syndrome coefficient calculation, polynomial multiplication, and parity vector generation. Each stage is handled by dedicated circuitry, which organizes the complex conversion process into manageable modules, reducing overall system complexity while enabling area reduction through efficient resource utilization.
Solution Approach 2:
The decoder employs dynamic circuitry that can be configured to handle different payload lengths and error correction requirements. The syndrome-to-parity conversion uses dynamic resource allocation where the same hardware resources are reconfigured based on the input payload size, reducing the need for static dedicated circuits for each payload length and thereby reducing total decoder area.
3Adaptability or versatility
If multiple payload lengths are supported, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal decoder architecture that can process multiple payload lengths (256-bit, 512-bit, 1024-bit, and variable lengths) using the same syndrome-to-parity conversion circuitry. The decoder dynamically adjusts its operation based on the input payload length, eliminating the need for multiple dedicated decoders and thereby reducing overall device complexity while maintaining high adaptability.
Solution Approach 2:
The decoder uses dynamic configuration to adapt to different payload lengths. Control logic dynamically adjusts the syndrome computation depth and parity conversion parameters based on the detected payload length, allowing a single decoder instance to handle multiple payload sizes without requiring separate hardwired circuits for each length, thus reducing device complexity.
Data Source
AI summary
Systems and methods for error location and error correction includes receiving, at a processor circuit, an input. The processor circuit generates a set of syndrome coefficients based on the input. The processor circuit generates a parity vector for the input based on the set of syndrome coefficients. The processor circuit determines a number of errors present in the input. Responsive to determining the number of errors present in the input, the processor circuit corrects the number of errors.