Shortened BCH and Reed-Solomon Decoder Reconfiguration for Lower Hardware

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Solution Overview

Problem

Existing error correction mechanisms for communication systems, particularly for shortened BCH codes and Reed-Solomon codes, face challenges in reducing hardware complexity while achieving high performance and efficient decoding, as prior solutions either focus on improving error location search or provide complex architectures that increase hardware requirements.

Innovation Solution

The proposed method uses a reverse error location polynomial and a modified Berlekamp-Massey algorithm to enable shared operation cells for syndrome computation and Chien search, reducing the number of finite-field constant multipliers and overall hardware complexity by re-configuring the decoder to use common operation cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate circuit configurations are used for syndrome calculator and Chien search cells, then each cell can process its specific inputs correctly, but hardware complexity is increased

Engineering Contradiction:
Improvedecoding accuracyVSAvoidhardware complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent makes the Chien search cells multi-functional by enabling them to perform both Chien search operations and syndrome calculations. The same circuit configuration processes different inputs (error location polynomial coefficients during Chien search, received polynomial coefficients during syndrome calculation) to produce the required outputs for both functions, thereby reducing hardware complexity while maintaining decoding accuracy

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces dynamic reconfiguration of the circuit based on operational phase. Control signals dynamically switch the function of the shared cells between Chien search mode and syndrome calculation mode, allowing the hardware to adapt its behavior to the current decoding stage without requiring separate dedicated circuits for each function

Inventive Principle:
Principle #15Dynamics

2Productivity

If more operation cells are used for parallel operation architecture, then decoding time is reduced, but hardware cost increases

Engineering Contradiction:
Improvedecoding rateVSAvoidhardware cost
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent makes the Chien search cells multi-functional by enabling them to perform both Chien search operations and syndrome calculations. The same circuit configuration processes different inputs (error location polynomial coefficients during Chien search, received polynomial coefficients during syndrome calculation) to produce the required outputs for both functions, thereby reducing hardware complexity while maintaining decoding accuracy

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces dynamic reconfiguration of the circuit based on operational phase. Control signals dynamically switch the function of the shared cells between Chien search mode and syndrome calculation mode, allowing the hardware to adapt its behavior to the current decoding stage without requiring separate dedicated circuits for each function

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS7941734B2Method and apparatus for decoding shortened BCH codes or reed-solomon codes
Publication Date: 2011.05.10 NAT CHIAO TUNG UNIV
  • US7941734B2 patent drawing
  • US7941734B2 patent drawing
  • US7941734B2 patent drawing

AI summary

The present invention proposes a method and apparatus for decoding BCH codes and Reed-Solomon codes, in which a modified Berlekamp-Massey algorithm is used to perform the decoding process and the efficiency of the decoder can be improved by re-defining the error locating polynomial as a reverse error locating polynomial, while the operation of the decoding process can be further realized by a common re-configurable module. Furthermore, the architecture of the decoder is consisted of a plurality of sets of re-configurable modules in order to provide parallel operations with different degrees of parallel so that the decoding speed requirement of the decoder in different applications can be satisfied.