BCH Error Correction Circuit with Switchable Decoding Capability

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Solution Overview

Problem

Existing error correction systems using Bose-Chaudhuri-Hocquenghem (BCH) codes have a fixed error correction capability determined by the size of the parity check matrix, limiting their adaptability to varying error conditions.

Innovation Solution

The error correction circuit extends the parity check matrix to include additional rows, generating additional parity and syndrome vectors, allowing it to switch between first and second error correction capabilities, thereby increasing the error correction capability dynamically.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the parity check matrix size is fixed to provide a predetermined error correction capability, then the system structure is simple, but the adaptability to varying error conditions deteriorates

Engineering Contradiction:
Improveerror correction capability adaptabilityVSAvoidparity check matrix structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The error correction circuit dynamically switches between first and second error correction capabilities based on error conditions. The decoder can perform either first error correction decoding using a first error correction capability or second error correction decoding using a second error correction capability, allowing the system to adapt its error correction strength to match the actual error severity in the data.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The error correction capability is segmented into multiple levels (first error correction capability and second error correction capability). The system divides the error correction function into discrete selectable modes, enabling the decoder to choose the appropriate correction strength rather than using a single fixed capability for all conditions.

Inventive Principle:
Principle #1Segmentation

2Reliability

If additional parity and syndrome vectors are generated to increase error correction capability, then data reliability is improved, but computational complexity increases

Engineering Contradiction:
Improvedata reliabilityVSAvoiddecoding process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system dynamically adjusts the decoding complexity by selecting between first error correction decoding and second error correction decoding based on the error conditions. When errors are detected, the system can activate the more complex second error correction decoding with additional parity and syndrome vectors to improve reliability, otherwise using the simpler first error correction capability.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The error correction capability parameter is changed based on error conditions. The system modifies the error correction strength by switching between different decoding modes, adjusting the level of parity checking and syndrome vector generation according to the actual error severity, thereby balancing reliability improvement with computational complexity.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11082068B2Error correction circuit, memory controller having error correction circuit, and memory system having memory controller
Publication Date: 2021.08.03 SK HYNIX INC
  • US11082068B2 patent drawing
  • US11082068B2 patent drawing
  • US11082068B2 patent drawing

AI summary

An error correction circuit using a BCH code may include a decoder performing at least one of a first error correction decoding using a first error correction capability or a second error correction decoding using a second error correction capability and an encoder generating a codeword based on a message and a generation matrix corresponding to the first error correction capability and generating an additional parity based on the codeword and one or more rows of a parity check matrix corresponding to the second error correction capability, wherein a syndrome vector generated based on a read vector corresponding to the codeword is used during the first error correction decoding and an additional syndrome generated based on the additional parity is used during the second error correction decoding, and wherein the one or more rows are extended from a parity check matrix corresponding to the first error correction capability.