BCJR Decoder Memory Storage Scheme for Low-Latency Iterative Decoding

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Solution Overview

Problem

Integrated circuit implementations of the BCJR algorithm for forward error correction face high latency and large memory requirements due to the need to process data from the beginning to the end and back, and store decoding information for extrinsic calculations, which limits their efficiency in wireless transmission systems.

Innovation Solution

A memory-efficient storage method (MESM) with shared memory storage and two-way metrics update, combined with module normalization and embedded storage, is used to reduce memory requirements and speed up the BCJR decoder, allowing parallel updates of forward and backward metrics and simplifying the decoding process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the BCJR algorithm processes data from beginning to end and back for iterative decoding, then decoding accuracy is improved, but latency increases

Engineering Contradiction:
Improvedecoding accuracyVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the decoding process into forward and backward passes, allowing independent parallel execution of metric calculations. By dividing the iterative decoding into separable forward (alpha) and backward (beta) metric computations, the system can process different segments simultaneously, reducing overall latency while maintaining the full iterative decoding accuracy of the BCJR algorithm.

Inventive Principle:
Principle #1Segmentation

2Reliability

If the BCJR decoder stores all decoding information for extrinsic information generation, then decoding accuracy is improved, but memory requirement increases

Engineering Contradiction:
Improvedecoding accuracyVSAvoidmemory requirement
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent extracts only the essential metric information (alpha and beta metrics) needed for extrinsic information calculation, discarding redundant intermediate decoding states. By extracting and storing only the critical metric values required for the BCJR algorithm's extrinsic information generation, the memory requirement is significantly reduced while preserving the full decoding accuracy that depends on these essential metrics.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If the BCJR algorithm performs forward and backward information gathering for each iteration, then decoding performance approaches Shannon limit, but computation complexity increases

Engineering Contradiction:
Improvedecoding performanceVSAvoidcomputation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent performs preliminary calculation and storage of alpha and beta metrics during the forward and backward passes, so that during extrinsic information generation, only simple combination operations are needed. By pre-computing and storing the metric values in advance, the complex iterative calculations are completed beforehand, reducing the computational complexity of each iteration while maintaining the near-Shannon-limit decoding performance.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8572470B2Memory-efficient storage method: a fast BJCR based decoder implementation scheme
Publication Date: 2013.10.29 NXP BV
  • US8572470B2 patent drawing
  • US8572470B2 patent drawing
  • US8572470B2 patent drawing

AI summary

A memory efficient, accelerated implementation architecture for BCJR based forward error correction algorithms. In this architecture, a memory efficiency storage scheme is adopted for the metrics and channel information to achieve high processing speed with a low memory requirement. Thus, BCJR based algorithms can be accelerated, and the implementation complexity can be 5 reduced. This scheme can be used in the BCJR based turbo decoder and LDPC decoder implementations.