Parallel BCJR Turbo Decoder With Banked Memory Routing
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Solution Overview
Problem
Conventional turbo decoders face limitations in increasing throughput due to the need for memory to process data blocks faster than decoding processors, which cannot be overcome by simply increasing processing speed, leading to inefficiencies in high-speed downlink packet access systems.
Innovation Solution
Implementing a turbo decoder with multiple BCJR processors operating in parallel, each paired with a respective interleaver, and utilizing non-overlapping memory banks within a single RAM module to enable simultaneous and efficient data processing and storage, preventing collisions through sorter circuits and routers that manage data block assignments and access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processing speed of the memory is increased to support parallel decoding processors, then the throughput of the turbo decoder is improved, but the cost and complexity of the memory system increases
Solution Approach 1:
The memory is divided into multiple non-overlapping memory banks (first memory bank, second memory bank, etc.) that can be accessed independently and simultaneously. This segmentation allows multiple decoding processors to write to different memory banks at the same time without causing address collisions, thereby increasing throughput without requiring faster memory processing speed.
Solution Approach 2:
The patent introduces a new dimension of parallelism by organizing memory into multiple banks that can be accessed concurrently. Instead of increasing the speed of a single memory resource, the system adds temporal parallelism through multiple independent memory access paths, effectively multiplying the throughput capacity without proportionally increasing memory speed requirements.
2Productivity
If multiple decoding processors operate in parallel to increase decoding speed, then the processing capacity is improved, but memory collisions occur when writing to the same address spaces
Solution Approach 1:
The memory address space is segmented into non-overlapping memory banks, where each decoding processor is assigned to write to a specific memory bank. This segmentation eliminates address collisions by ensuring that simultaneous writes from multiple processors target different physical memory regions, maintaining reliability while enabling parallel processing.
Solution Approach 2:
Sorter circuits are introduced as intermediary components that manage the assignment of decoded data to appropriate memory banks. These sorters receive data from multiple decoding processors and route each data block to its designated non-overlapping memory bank, preventing collisions and ensuring orderly parallel access.
3Productivity
If the number of memory modules is increased to support higher throughput, then the data storage capacity is improved, but the device complexity and cost increase
Solution Approach 1:
Instead of using multiple separate memory modules, the patent segments a single memory module into multiple non-overlapping banks. This internal segmentation provides the same parallel access capability as multiple modules would offer, but without the increased complexity and cost of managing multiple independent memory devices.
Solution Approach 2:
The patent combines multiple memory access functions into a single memory module by implementing multiple non-overlapping banks within one device. This merging approach achieves the throughput benefits of multiple memory modules while reducing the quantity of hardware components, simplifying the overall system architecture.
Data Source
AI summary
A turbo decoder has at least two Bahl, Cocke, Jelinek, and Raviv (BCJR) processors in parallel, each in serial communication with respective interleavers. The BCJR processors and interleavers are in communication with a memory module that is internally split into non-overlapping memory banks. The turbo decoder includes respective sorter circuits in communication with the output of each BCJR processor/interleaver. A sorter circuit receives a data block from a BCJR processor/interleaver and directs the data block to the memory bank designated by an address assigned to the data block by an interleaver.