BD PWM Circuit With Common-Mode Hopping for Low Idle Current
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Solution Overview
Problem
Conventional class D amplifiers using BD type pulse width modulation (PWM) face issues with high power consumption due to high duty ratio of common mode signals in light load conditions, leading to increased ripple current and idle current, and distortion of output signals.
Innovation Solution
A BD type PWM circuit with adaptive common mode voltage hopping, utilizing a duty ratio adjustment circuit to generate intermediate PWM signals, including basic, offset, and heavy load signals, which selects between these based on load conditions to minimize power consumption and maintain signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional BD type PWM modulation is used in light load condition, then the modulation can reduce the demand for output filter, but the duty ratio of common mode signal reaches 50% causing high ripple current and high idle current
Solution Approach 1:
The patent implements dynamic common mode voltage hopping by switching between a first common mode voltage (first duty ratio) and a second common mode voltage (second duty ratio) based on load conditions. The control circuit dynamically adjusts which common mode voltage is applied to the bridge legs during specific time periods, enabling the system to adapt to varying load requirements and minimize power consumption while maintaining modulation effectiveness.
2Loss of energy
If asymmetrical driving approach is adopted to reduce common mode signal ripple current, then the ripple current can be reduced, but the duty ratio of differential mode signal becomes distorted
Solution Approach 1:
The patent employs periodic switching between different common mode voltages applied to different bridge legs during specific time periods within each switching cycle. This periodic action creates a structured pattern of voltage application that reduces ripple current while maintaining signal integrity through controlled asymmetry that is reset each cycle.
Solution Approach 2:
The patent changes the common mode voltage parameter applied to bridge legs based on operating conditions. By switching between a first common mode voltage and a second common mode voltage, the system adjusts the voltage parameters dynamically to reduce ripple current while preventing signal distortion through controlled parameter variation.
3Loss of energy
If non-linear level adjustment is executed on input signals to decrease common mode signal duty ratio, then the duty ratio can be decreased in light load condition, but distortion of differential mode signal occurs
Solution Approach 1:
The patent introduces common mode voltage as an intermediary parameter that mediates between the input signals and the output PWM signals. By controlling the common mode voltage applied to bridge legs rather than directly adjusting input signal levels, the system reduces idle current while avoiding the distortion that would result from non-linear level adjustment of the input signals themselves.
Data Source
AI summary
A BD type pulse width modulation (PWM) circuit is configured to convert a pair of complementary input signals to a pair of output PWM signals. The BD PWM circuit modulates a basic modulation signal according to the pair of input signals, to generate a basic PWM signal. The common mode levels of the pair of input signals and the basic modulation signal are the same. The BD PWM circuit modulates an offset modulation signal according to the pair of input signals to generate an offset PWM signal. The offset modulation signal and the basic modulation signal have a non-zero offset in between. The BD PWM circuit selects the offset PWM signal or a heavy load PWM signal as the pair of output PWM signals. The heavy load PWM signal is correlated with the basic PWM signal.