Binary Decision Diagram Synthesis with Inverted Edges
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Solution Overview
Problem
Current methods for formal and semiformal verification of digital circuit designs are resource-intensive and inefficient, particularly when dealing with binary decision diagrams that include inverted edges and quantifiable as well as nonquantifiable variables, leading to exponential computational resources and incomplete verification coverage as design size increases.
Innovation Solution
A method for synthesizing binary decision diagrams by building a gate representing an OR function of selected parent paths and iteratively accumulating a synthesized gate set, which reduces the size of the design representation while maintaining behavioral equivalence, using a parametric reduction toolkit to identify and replace cut gates with simpler logic, thereby reducing the number of RANDOM gates and improving verification efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If formal verification techniques are used to ensure design correctness, then reliability is improved, but computational resources increase exponentially with design size
Solution Approach 1:
The verification process is segmented into multiple passes: a first pass performs exhaustive formal verification on a subset of design elements, while a second pass uses simulation-based techniques on remaining elements. This segmentation allows the system to achieve comprehensive verification coverage without requiring exponential computational resources for the entire design at once.
Solution Approach 2:
The patent applies partial formal verification to critical subsets of the design rather than attempting complete formal verification of the entire design. By focusing formal verification efforts on high-risk or high-importance components, the system achieves sufficient reliability assurance without the exponential resource cost of full formal verification.
2Adaptability or versatility
If design size increases to meet functional requirements, then adaptability is improved, but verification coverage decreases
Solution Approach 1:
The design is divided into multiple verification domains or partitions, each verified using appropriate techniques. This segmentation enables the verification system to scale with design size by processing larger designs through multiple manageable verification passes rather than requiring complete verification of the entire design simultaneously.
Solution Approach 2:
The patent dynamically adjusts verification parameters such as the depth of formal verification, the selection of verification targets, and the allocation of computational resources based on design size and complexity. This allows verification coverage to be maintained at acceptable levels even as design size increases.
Data Source
AI summary
A method, system and computer program product for performing synthesis of representations is disclosed. The method comprises receiving a representation of a relation and building a gate representing an OR function of one or more selected parent paths into a node of said representation of said relation. A synthesized gate for said gate representing said OR function and synthesis of a set of representations of relations by iterating said building step and said creating step over one or more variables in said representation of said relation is performed to accumulate a synthesized gate set, which synthesized gate set is returned.