Hardware Beacon Processor for VoWLAN Power Management
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Solution Overview
Problem
Current data communication devices, especially those with dual-core architectures, face complexity and high costs due to the need for digital signal processors (DSPs) for real-time processing, which are expensive and power-intensive, making single-processor solutions inefficient for voice over Internet Protocol (VoIP) and voice over wireless local area network (VoWLAN) communications.
Innovation Solution
Implementing a hardware-centric medium access control (MAC) device with a packet receiver and beacon processor that filters unwanted packets without requiring a microprocessor, allowing for VoIP and VoWLAN communications using a single RISC microprocessor, eliminating the need for a dedicated DSP and optimizing data processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a software MAC is implemented on a single processor, then device complexity is reduced, but real-time processing performance deteriorates due to interrupt conflicts with other applications
Solution Approach 1:
The patent segments the processor functions by dedicating specific time slots and interrupt priorities to MAC operations. The software MAC is divided into time-critical interrupt service routines and non-critical background processing, allowing real-time requirements to be met without requiring a separate processor.
Solution Approach 2:
The patent implements preliminary action by pre-configuring interrupt priority levels and time slot allocations for MAC operations before runtime. This ensures that real-time MAC processing can proceed without conflict with other applications, as the scheduling framework is established in advance.
2Reliability
If a dual-core architecture with DSP is used, then real-time processing capability is improved, but device cost and power consumption increase
Solution Approach 1:
The patent makes the single processor universal by implementing a software MAC that can handle both real-time communication protocols and general-purpose computing tasks. The processor is configured to perform multiple functions including MAC processing, application execution, and power management, eliminating the need for dedicated DSP hardware.
Solution Approach 2:
The patent substitutes the mechanical hardware-based DSP system with a software-based MAC implementation. Instead of using dedicated digital signal processing hardware, the patent implements MAC functionality as software running on a general-purpose processor, reducing hardware complexity while maintaining real-time performance through optimized interrupt handling.
3Reliability
If a dual-core architecture with DSP is used, then real-time processing capability is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action through time-slot-based MAC processing, where the processor alternates between MAC interrupt handling and other applications in predetermined time intervals. This periodic scheduling allows the processor to enter low-power states between active processing periods, reducing overall power consumption compared to continuous operation of dedicated DSP hardware.
Data Source
AI summary
A battery-powered WLAN communication device has an activity sensor operable to identify an available packet. A PHY module is awakened to begin receiving the packet. The PHY module decodes a full MAC address from a MAC portion of a header of the packet. A MAC address parser receives the MAC address and determines whether the packet is to be received by comparing the full MAC address to a MAC address of the WLAN communication device. The MAC address parser is awakened to perform the comparing and shutdown after. Packets to be received include beacon packets. A hardware centric MAC separate from the MAC address parser has a beacon processor capable of being awakened from a shutdown state to process a beacon packet. The PHY module, the MAC address parser, and the beacon processor module are operable to be awakened and shutdown independently of each other and of a microprocessor.