Beaded Fin Transistor Gate Control
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Solution Overview
Problem
Current transistor configurations, such as finned and gate-all-around (GAA) transistors, face challenges in maintaining gate control and are plagued by parasitic capacitance issues as they scale, with GAA configurations introducing process complexity and finned configurations offering inadequate gate control.
Innovation Solution
The formation of beaded fin transistors through a multilayer finned structure with selectively etched narrower portions, which increases gate surface area and mitigates parasitic capacitance by maintaining the structure's integrity, allowing for improved gate control and quantum confinement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If finned transistor configuration is used, then manufacturing is simpler compared to GAA, but gate control is inadequate
Solution Approach 1:
The channel region is segmented into multiple discrete fins arranged vertically, with each fin providing an independent conduction path. This segmentation allows the gate to control multiple channels simultaneously while maintaining the structural simplicity of individual fins, thus improving gate control without significantly complicating manufacturing
Solution Approach 2:
The invention transitions from a planar 2D channel structure to a 3D vertical fin array structure. By stacking multiple fins vertically, the gate controls channels in three dimensions, increasing the effective gate-controlled channel area and improving gate control effectiveness while maintaining manufacturing simplicity
2Reliability
If gate-all-around (GAA) configuration is used, then gate control is improved, but process complexity increases
Solution Approach 1:
Instead of implementing a continuous gate-all-around structure, the invention segments the channel into multiple discrete fins. Each fin is independently formed and controlled, simplifying the fabrication process while collectively providing enhanced gate control through the combined effect of multiple gate-controlled channels
Solution Approach 2:
Rather than forming a gate that completely surrounds each channel (GAA approach), the invention inverts the approach by forming multiple vertical fins with gates positioned to control the sides and top of each fin. This alternative configuration achieves superior gate control with reduced process complexity
3Productivity
If transistor scaling is continued, then device density increases, but parasitic capacitance problems worsen
Solution Approach 1:
By transitioning to a vertical 3D fin structure, the invention increases device density in the vertical dimension while maintaining larger spacing between adjacent transistor structures in the horizontal plane. This dimensional transition allows higher density without proportionally increasing parasitic capacitance, as the gate-controlled channel area increases more rapidly than the parasitic capacitance
Data Source
AI summary
Techniques are disclosed for forming a beaded fin transistor. As will be apparent in light of this disclosure, a transistor including a beaded fin configuration may be formed by starting with a multilayer finned structure, and then selectively etching one or more of the layers to form at least one necked (or relatively narrower) portion, thereby forming a beaded fin structure. The beaded fin transistor configuration has improved gate control over a finned transistor configuration having the same top down area or footprint, because the necked/narrower portions increase gate surface area as compared to a non-necked finned structure, such as finned structures used in finFET devices. Further, because the beaded fin structure remains intact (e.g., as compared to a gate-all-around (GAA) transistor configuration where nanowires are separated from each other), the parasitic capacitance problems caused by GAA transistor configurations are mitigated or eliminated.