Charged Particle Beam Deflection Time Estimation Using Subfield Pattern Maps

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Solution Overview

Problem

Existing charged particle beam writing technologies inaccurately estimate the time required for beam deflection between subfields due to the inclusion of skipped subfields in the writing time calculation, leading to increased errors in estimated writing time compared to actual writing time.

Innovation Solution

A charged particle beam writing apparatus and method that accurately distinguish and count subfields with patterns from those without, using a mesh region setting and merging process to generate a region number map for precise deflection time estimation, incorporating a storage system, processing circuitry, and multiple stage deflection mechanism.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the beam traveling time is calculated based on multiplying divided chip size by divided SF size, then the calculation is simple, but the estimated writing time has large errors because skipped SFs are included

Engineering Contradiction:
Improvecalculation simplicityVSAvoidwriting time estimation accuracy
Core Design Contradiction:
Ease of manufactureVSMeasurement precision

Solution Approach 1:

The patent performs preliminary classification of subfields into pattern SFs and empty SFs before calculating beam traveling time. By pre-identifying which SFs contain patterns using writing data analysis, the system can exclude empty SFs from the traveling time calculation, thereby improving accuracy without significantly complicating the overall process

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the chip region into multiple subfields (SFs) and further categorizes them into pattern SFs and empty SFs. This segmentation allows the system to calculate beam traveling time only between relevant SFs that contain patterns, rather than treating all SFs uniformly, thus improving estimation accuracy

Inventive Principle:
Principle #1Segmentation

2Device complexity

If all SFs are treated equally in writing time calculation, then the calculation method is simple, but the error between estimated and actual writing time increases

Engineering Contradiction:
Improvecalculation method complexityVSAvoidwriting time estimation reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent applies different treatment to different types of SFs based on their local characteristics. Pattern SFs are included in traveling time calculations while empty SFs are excluded. This local differentiation approach improves the reliability of writing time estimation by accounting for the actual beam movement requirements in different regions of the chip

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables highly accurate calculation of deflection time and writing time by differentiating patterned and empty subfields, reducing the error between estimated and actual writing times, thereby improving the precision of the writing process.

Implementation Method 1

a beam position is deflected to an SF by one deflector of multiple stage deflector, and the beam position is deflected to a pattern forming position in the SF concerned by another deflector

Methodology Applied
Scientific EffectElectromagnetic deflection: Lorentz Force

Data Source

PatentUS9734981B2Charged particle beam writing apparatus and charged particle beam writing method
Publication Date: 2017.08.15 NUFLARE TECH INC
  • US9734981B2 patent drawing
  • US9734981B2 patent drawing
  • US9734981B2 patent drawing

AI summary

A charged particle beam writing apparatus includes a circuitry to set, when a charged particle beam is deflected to move between plural small regions by a deflector, plural first mesh regions obtained by virtually dividing a chip region into regions by length and width sizes same as those of each of the plural small regions; determine whether a shot figure having been assigned exists in each of the plural first mesh regions; a circuitry to perform, for the plural first mesh regions, merging of two or more adjacent first mesh regions; a circuitry to measure, for each of plural second mesh regions each obtained by merging, the number of first mesh regions each having been determined that an assigned shot figure exists therein; and a circuitry to generate a map for each chip, where measured number of first mesh regions with the shot figure is defined as a map value.