Charged Particle Beam Scanning Module for Real-Time DAC INL Correction
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Solution Overview
Problem
Existing charged particle beam devices face challenges in correcting integral non-linearity errors (INL errors) in digital-to-analog conversion circuits (DAC circuits) in real time, leading to reduced throughput and impaired image uniformity due to environmental changes.
Innovation Solution
A charged particle beam scanning module and device that includes a scanning controller, DAC circuit, and an analog-to-digital conversion (ADC) circuit with different sampling frequencies, allowing for real-time correction of INL errors by evaluating the output characteristic of the DAC circuit using the ADC circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the ADC circuit operates at the same high sampling frequency as the DAC circuit to enable real-time correction, then the INL error correction accuracy is improved, but the conversion operation cannot keep up with the high-speed digital signal changes
Solution Approach 1:
The patent applies dynamics by making the sampling frequency adaptable rather than fixed. The ADC circuit's sampling frequency is dynamically adjusted based on the operational mode: it operates at a lower frequency during normal scanning and automatically increases to a higher frequency when correction mode is activated, allowing the system to optimize between speed and precision as needed
Solution Approach 2:
The patent implements periodic action by alternating between normal scanning operation and correction operation in periodic cycles. The correction operation is performed periodically at predetermined intervals, allowing the ADC circuit to operate at high frequency only when needed for correction, while maintaining high-speed scanning during normal operation
2Measurement precision
If the system performs correction operation at low speed to accommodate ADC conversion time, then the INL error correction is achieved, but the throughput of the charged particle beam device is reduced
Solution Approach 1:
The patent segments the operation into distinct functional modes: normal scanning mode for high-speed imaging and correction mode for precision calibration. By separating these functions temporally and operationally, the system can maintain high throughput during scanning while achieving accurate correction during dedicated correction periods
Solution Approach 2:
The patent ensures continuity of useful action by maintaining high-speed scanning operation during normal mode and only temporarily reducing speed during brief correction intervals. The majority of operational time is spent in high-productivity scanning mode, ensuring overall throughput is preserved while still achieving necessary corrections
3Reliability
If the ADC circuit sampling frequency is increased to match DAC frequency, then real-time correction capability is improved, but the conversion operation cannot follow high-speed digital signal changes
Solution Approach 1:
The system dynamically adjusts the ADC sampling frequency based on operational requirements. During normal scanning, the ADC operates at a lower frequency that maintains signal tracking capability. When correction mode is activated, the ADC frequency dynamically increases to match the DAC frequency, enabling real-time correction without compromising normal scanning performance
Data Source
AI summary
A charged particle beam scanning module, a charged particle beam device, and a computer that can correct an INL error in a DAC circuit in real time. The charged particle beam scanning module includes a scanning controller configured to output a scanning digital signal of a charged particle beam, a DAC circuit configured to convert the scanning digital signal into a scanning analog signal and output the scanning analog signal, and an ADC circuit configured to convert the scanning analog signal into an evaluation digital signal. A sampling frequency at which the DAC circuit samples the scanning digital signal is a first frequency, and a sampling frequency at which the ADC circuit samples the scanning analog signal is a second frequency smaller than the first frequency. The scanning controller determines an output characteristic of the DAC circuit by evaluating the scanning digital signal and the evaluation digital signal.