Beam Selection Hardware Accelerator for 5G Scheduling Deadlines
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Solution Overview
Problem
Existing wireless communication systems face challenges in efficiently selecting beams for data scheduling due to the computational intensity and time constraints of beam selection algorithms, particularly in 5G networks with massive MIMO and shorter transmission time intervals, which can overwhelm low-power CPU cores like ARM cores.
Innovation Solution
Implementing a beam selection hardware accelerator, such as field programmable gate arrays (FPGAs), to offload computationally intensive beam selection tasks from processors, allowing for faster and more power-efficient scheduling operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If beam selection algorithms are implemented on low-power CPU cores (e.g., ARM cores), then power consumption is reduced, but computational intensity causes time delays and inability to meet scheduling deadlines
Solution Approach 1:
The system is divided into two parts: a low-power CPU core for control functions and a dedicated hardware accelerator for computationally intensive beam selection tasks. This segmentation allows each component to operate in its optimal performance and power consumption regime, resolving the contradiction between low power consumption and high scheduling speed.
Solution Approach 2:
A hardware accelerator acts as an intermediary component between the CPU and the beam selection process. It offloads computationally intensive operations from the CPU, enabling fast beam selection while allowing the CPU to maintain low power consumption for control functions.
2Device complexity
If beam selection algorithms are implemented on low-power CPU cores (e.g., ARM cores), then device complexity is reduced, but computational intensity causes time delays and inability to meet scheduling deadlines
Solution Approach 1:
The system segments functionality between a simple low-power CPU and a specialized hardware accelerator. The CPU handles control logic while the hardware accelerator performs computationally intensive beam selection, reducing time delays without significantly increasing overall device complexity.
Solution Approach 2:
The patent replaces software-based beam selection algorithms running on the CPU with a hardware-based accelerator. This substitution of mechanical/computational approach dramatically reduces processing time for beam selection while keeping the CPU simple and low-complexity.
3Ease of manufacture
If beam selection algorithms are implemented on low-power CPU cores (e.g., ARM cores), then ease of manufacture is improved, but computational intensity causes time delays and inability to meet scheduling deadlines
Solution Approach 1:
The system segments functionality between a standard low-power CPU (easy to manufacture and integrate) and a dedicated hardware accelerator for beam selection. This allows the CPU to remain simple and easy to manufacture while the accelerator handles high-speed computational tasks.
Solution Approach 2:
The hardware accelerator is designed as a universal component that can be integrated with standard low-power CPU cores. This multi-functional approach allows the same CPU architecture to be used across different implementations while the accelerator provides the necessary computational boost for meeting scheduling deadlines.
Data Source
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AI summary
An apparatus includes a beam selection hardware accelerator for determining a set of beams to be used for data scheduling by a wireless node for a transmission time interval, the beam selection hardware accelerator being configured to: receive a beam information and information indicating an angular separation of beams for a set of selected beams; create a graph based on the beam information and the minimum angular separation; select a set of beams, out of a plurality of beams, as a maximum weight independent set of beams based on the created graph; and provide a notification of the selected set of beams.