Beam-Shaped Semiconductor Layer for Non-Volatile Memory
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Solution Overview
Problem
The reduction in channel dimensions of planar transistors leads to short-channel effects in non-volatile memory devices, causing high electric fields and lateral charge leakage, which affects the functionality of memory cells.
Innovation Solution
A beam-shaped semiconductor layer is used with a charge-trapping stack that covers its lateral surfaces, embedding the layer in a U-shaped form to improve electrostatic charge control and reduce short-channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel length is reduced to increase memory device density, then the device density is improved, but short-channel effects worsen causing high electric fields and lateral charge leakage
Solution Approach 1:
The patent transitions from a planar transistor layout to a vertically stacked three-dimensional architecture. The channel region is formed as a beam-shaped structure extending in the first direction, with the memory element stacked vertically between the channel and gate. This vertical stacking in the third dimension allows for improved electrostatic control while maintaining a compact footprint, effectively resolving the contradiction between device density and short-channel effects.
Solution Approach 2:
The memory element is embedded within the beam-shaped channel region, with the charge-trapping stack positioned inside the channel structure. The gate wraps around the channel region, creating a nested configuration where the memory element is contained within the channel, which itself is surrounded by the gate. This nested arrangement improves electrostatic control by bringing the gate closer to the channel in multiple directions.
2Length of moving object
If the channel dimensions are aggressively scaled down, then the device size is reduced, but the electric field between source and drain becomes too high causing lateral charge leakage
Solution Approach 1:
The memory element is embedded within the beam-shaped channel region, with the charge-trapping stack positioned inside the channel structure. The gate wraps around the channel region, creating a nested configuration where the memory element is contained within the channel, which itself is surrounded by the gate. This nested arrangement improves electrostatic control by bringing the gate closer to the channel in multiple directions.
Solution Approach 2:
The memory element comprises a composite charge-trapping stack structure with multiple layers including a first insulator layer, a charge-trapping layer, and a second insulator layer. This composite structure provides both charge storage capability and electrostatic control, helping to manage the electric field in the scaled-down channel region and prevent lateral charge leakage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces short-channel effects, enhancing the electrostatic charge control and maintaining the memory function of the non-volatile memory device, even at aggressively scaled dimensions.
Implementation Method 1
the memory element comprising a charge-trapping stack which covers on said lateral surfaces at least the lower surface directed towards the semiconductor surface layer and the side surfaces which are directly connecting to the lower surface so as to embed the beam-shaped semiconductor layer in a U-shaped form of the charge-trapping stack
Data Source
AI summary
According to certain embodiments, a non-volatile memory device on a semiconductor substrate having a semiconductor surface layer comprises a channel region that extends in a first direction between the source and drain regions. The gate is disposed near the channel region and the memory element is disposed in between the channel region and the gate. The channel region is disposed within a beam-shaped semiconductor layer, with the beam-shaped semiconductor layer extending in the first direction between the source and drain regions and having lateral surfaces extending parallel to the first direction. The memory element comprises a charge-trapping stack so as to embed therein the beam-shaped semiconductor layer in a U-shaped form.