Beat-Frequency PLL Locking With Dynamic Bit-Width Switching
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Solution Overview
Problem
Conventional Phase-Locked Loops (PLLs) face challenges in achieving high speed, accuracy, larger range, lower jitter, and lower power simultaneously, particularly in fractional-N PLLs, due to limitations in frequency resolution and power consumption.
Innovation Solution
The implementation of a beat-frequency PLL architecture with a modulo-K counter and phase predictor, allowing multiple frequency lock ranges to reduce bit width and power consumption, while ensuring accurate frequency locking by switching between different bit widths and frequency lock ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional PLL architecture is used with high multiplication factor to achieve high output frequency, then output frequency range is improved, but power consumption increases and frequency resolution deteriorates
Solution Approach 1:
The frequency multiplication process is segmented into two stages: a first modulo-K counter for coarse frequency multiplication and a second counter for fine frequency adjustment. This segmentation allows the system to achieve high output frequencies without requiring a single high-speed counter to operate at the full multiplication rate, thereby reducing power consumption while maintaining frequency range.
Solution Approach 2:
The system dynamically switches between different counter configurations and bit widths based on the required output frequency and resolution. The first modulo-K counter operates with a fixed K value for coarse multiplication, while the second counter dynamically adjusts its bit width to provide fine frequency control, optimizing power consumption across different operating conditions.
2Measurement precision
If higher bit width counters are used to improve frequency resolution, then frequency resolution is improved, but power consumption and device complexity increase
Solution Approach 1:
Frequency resolution is achieved through segmentation of the counting process into two stages: the first modulo-K counter provides coarse frequency division with fixed bit width, while the second counter provides fine frequency adjustment with dynamically adjustable bit width. This allows high frequency resolution to be achieved without requiring a single high-bit-width counter operating at full speed, thereby reducing power consumption.
Solution Approach 2:
The system changes the bit width parameter of the second counter dynamically based on the required frequency resolution and operating conditions. By adjusting the bit width of the second counter rather than using a fixed high-bit-width counter throughout, the system achieves high frequency resolution only when needed, optimizing power consumption across different operating modes.
3Adaptability or versatility
If single frequency lock range is used to simplify design, then device complexity is reduced, but adaptability to different frequency ranges deteriorates
Solution Approach 1:
The system dynamically configures the counter parameters including K value and bit widths based on the target output frequency and required frequency resolution. The controller adjusts the first modulo-K counter's K value and the second counter's bit width dynamically, allowing the same hardware architecture to adapt to different frequency lock ranges without requiring multiple dedicated counter configurations.
Solution Approach 2:
The dual-counter architecture provides universal functionality by combining a first modulo-K counter for coarse frequency multiplication with a second counter for fine frequency adjustment. This universal structure can accommodate different frequency lock ranges and resolution requirements through dynamic parameter configuration, eliminating the need for multiple specialized counter designs.
Data Source
AI summary
A PLL has a controlled oscillator with a limited frequency range. It has a phase accumulator and a phase predictor whose ranges are limited to a value K related to their bit width. K is less than the ratio of the maximum output frequency and the minimum reference frequency. The PLL locks the output frequency to a value higher than the FCW times the reference frequency. The PLL includes a means for setting the output frequency to a target frequency before achieving final lock. The PLL may have a lock detector. After acquiring lock, the PLL may reduce the bit width and K value, for example by cutting power to or switching off some of the bits, or by switching off slow counters in a multi-counter system.