Behavioral Synthesis Apparatus Pipeline Delay Constraint
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Solution Overview
Problem
Existing behavioral synthesis systems face challenges in generating RTL code with high throughput, as stricter delay constraints either increase the number of pipeline stages without improving throughput in pipeline circuits or deteriorate throughput in multi-state circuits.
Innovation Solution
A behavioral synthesis apparatus that determines whether to convert a loop description into a pipeline and sets a stricter delay constraint for pipeline conversions than for non-pipeline conversions, optimizing the number of pipeline stages and execution cycles to enhance processing capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a loop description is synthesized as a pipeline circuit with stricter delay constraint, then the number of pipeline stages increases, but the throughput does not improve because the number of execution cycles remains unchanged
Solution Approach 1:
The patent dynamically adjusts the delay constraint based on the synthesis type. For pipeline circuits, a first (stricter) delay constraint is applied, while for multi-state circuits, a second (relaxed) delay constraint is applied. This dynamic adjustment allows the system to optimize for pipeline depth when appropriate while avoiding excessive execution cycle increases in multi-state circuits, thereby improving throughput without unnecessary pipeline stage proliferation.
Solution Approach 2:
The patent changes the delay constraint parameter according to the circuit synthesis type. By setting different delay constraint values for pipeline versus multi-state synthesis, the system can control the trade-off between pipeline stage count and execution cycle count, resolving the contradiction where stricter delays increase pipeline stages but fail to improve throughput.
2Speed
If a loop description is synthesized as a multi-state circuit with stricter delay constraint, then the number of pipeline stages increases, but the number of execution cycles increases causing throughput deterioration
Solution Approach 1:
The patent dynamically switches between different delay constraint strategies based on the synthesis type. When synthesizing multi-state circuits, it applies a relaxed delay constraint (second value) that prevents excessive pipeline stage insertion, thereby avoiding the increase in execution cycles that would deteriorate throughput. This dynamic adaptation resolves the contradiction by selecting appropriate constraints for each synthesis mode.
Solution Approach 2:
The patent changes the delay constraint parameter from a first value (for pipeline) to a second value (for multi-state) based on the synthesis type. This parameter change ensures that multi-state circuits do not suffer from excessive pipeline staging, which would increase execution cycles and reduce throughput, while still allowing pipeline circuits to benefit from stricter timing constraints.
3Ease of manufacture
If a uniform delay constraint is applied to both pipeline and multi-state circuits, then the synthesis process is simplified, but the throughput cannot be optimized for both circuit types
Solution Approach 1:
The patent applies different delay constraint values to different synthesis types (pipeline versus multi-state) based on their specific requirements. This localized quality approach allows pipeline circuits to use stricter constraints for better timing closure while multi-state circuits use relaxed constraints to avoid excessive execution cycles, thereby optimizing throughput for each circuit type without complicating the overall synthesis process.
Solution Approach 2:
The patent changes the delay constraint parameter based on the synthesis type being performed. By detecting whether the current synthesis is for pipeline or multi-state circuit, the system automatically selects the appropriate delay constraint value, enabling throughput optimization for both circuit types while maintaining a unified synthesis framework that does not require separate synthesis processes.
Data Source
AI summary
A behavioral synthesis apparatus includes a determination unit that determines whether or not a loop description should be converted into a pipeline, and a synthesis unit that performs behavioral synthesis while setting a stricter delay constraint for a loop description that is converted into a pipeline than a loop description that is not converted into a pipeline.