Behavioral Synthesis Test Bench for Simulation Equivalence

The patent introduces a test bench as an intermediary component that mediates between the test vector and the RTL circuit. The test bench generates timing signals that control when inputs are applied and when outputs are observed, bridging the gap between behavioral and RTL simulation timing domains. This allows the same test vector to be used while accounting for timing differences through the test bench's control logic.

The patent changes the timing parameters of the simulation by generating dynamic timing signals that control input application and output observation. Instead of using fixed timing assumptions, the system adjusts timing parameters based on the actual circuit behavior and synthesis results, allowing accurate comparison between behavioral and RTL simulations.

The patent segments the simulation process into two distinct modes: equivalence verification mode and performance measurement mode. In equivalence verification, timing is synchronized between behavioral and RTL simulations. In performance measurement, the focus shifts to measuring actual RTL circuit timing characteristics. This segmentation allows both goals to be achieved without compromise.

The test bench employs dynamic timing signals that can adapt their behavior based on the simulation mode. The timing signals are generated dynamically rather than being fixed, allowing the system to switch between synchronized timing for equivalence checking and asynchronous timing for performance measurement, making the verification system flexible and multi-functional.