Back-End-of-Line Memory Architecture With Segmented Bitlines
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Solution Overview
Problem
Conventional memory devices face challenges such as increased bitline capacitance, reduced read yield, tighter interconnect pitch, and higher processing costs due to the increasing capacity of memory devices, which limits scalability and memory density.
Innovation Solution
The proposed solution involves dividing multiple memory cells of a bitline into smaller sets, each coupled to a selector to control access, reducing capacitance and improving access speed, while using thin-film transistors (TFTs) to minimize additional process costs and eliminate the need for tight pitch interconnect layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory device capacity is increased, then memory density is improved, but bitline capacitance increases and read yield decreases
Solution Approach 1:
The memory array is divided into multiple banks, with each bank having its own dedicated bitline. This segmentation isolates the capacitance load to smaller groups of memory cells per bitline, reducing the total capacitance that affects read yield while maintaining high overall memory density through the banked structure.
2Quantity of substance
If memory device capacity is increased, then memory density is improved, but interconnect pitch becomes tighter and processing cost increases
Solution Approach 1:
Multiple memory banks share common wordlines and other interconnect structures. This merging approach reduces the total number of interconnect lines required compared to completely independent banks, thereby reducing interconnect pitch requirements and lowering processing costs while achieving high memory density through vertical stacking of banks.
Solution Approach 2:
The patent employs three-dimensional stacking of memory banks vertically above the substrate. This vertical dimensionality change allows high memory density to be achieved without proportionally increasing the lateral interconnect pitch, thereby avoiding the need for tighter interconnect spacing and reducing processing complexity and cost.
3Quantity of substance
If memory device capacity is increased, then memory density is improved, but scalability is limited
Solution Approach 1:
The memory architecture uses universal, standardized memory bank units that can be replicated and scaled. Each bank follows the same structure with a selector, storage cell, and bitline, allowing systematic scaling of memory capacity by adding more banks without changing the fundamental design, thereby improving scalability.
Solution Approach 2:
By stacking memory banks vertically in three dimensions rather than expanding only in the lateral plane, the architecture achieves scalability without proportionally increasing the footprint or interconnect complexity. This vertical scaling approach maintains manufacturing feasibility and design uniformity as capacity increases.
Data Source
AI summary
Embodiments herein describe techniques for a semiconductor device including a substrate. A first set of memory cells and a first selector are formed within a first group of metal layers and inter-level dielectric (ILD) layers above the substrate. A second set of memory cells and a second selector are formed within a second group of metal layers and ILD layers above the first group of metal layers and ILD layers. The first selector is coupled to the first set of memory cells to select one or more memory cells of the first set of memory cells based on a first control signal. In addition, the second selector is coupled to the second set of memory cells to select one or more memory cells of the second set of memory cells based on a second control signal. Other embodiments may be described and/or claimed.