Belief Propagation Network Layout for Low-Complexity FEC Routing
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Solution Overview
Problem
Current interconnection networks for Forward Error Correction (FEC) encoders and decoders, such as Benes and Clos networks, face complexity in routing algorithms and hardware requirements, leading to inefficiencies in high-speed data processing, especially in telecommunications and earth observation applications.
Innovation Solution
An interconnection network with M stages, where each stage includes switching elements with specific input and output pins, allowing for efficient routing of input values to output terminals with circular shifts, optimized for non-prime integer inputs, reducing hardware complexity and enabling real-time self-routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If Benes or Clos networks are used for interconnection in FEC encoders and decoders, then routing capability and connectivity are improved, but device complexity and hardware requirements increase
Solution Approach 1:
The patent segments the interconnection network into multiple stages (M stages) with each stage containing simpler switching elements. This segmentation allows the complex routing function to be distributed across multiple simpler components, reducing the complexity of individual elements while maintaining overall routing capability. The network processes data through sequential stages rather than requiring a single complex switching fabric.
Solution Approach 2:
The patent introduces dynamic routing commands that are applied to switching elements at each stage, enabling the network to adaptively route data based on real-time requirements. The routing commands allow the network to perform circular shifts and dynamic reconfiguration, providing versatility without requiring a statically complex hardware structure. This dynamic approach enables the same hardware to handle multiple routing patterns.
2Productivity
If traditional interconnection networks are used for high-speed data processing, then connectivity is improved, but processing time and hardware complexity increase
Solution Approach 1:
The patent performs preliminary routing decisions at each stage based on pre-computed routing commands. The routing commands are prepared in advance and applied systematically through the M stages, allowing data to be routed efficiently without real-time computation delays. This preliminary action reduces processing time by eliminating on-the-fly routing calculations.
Solution Approach 2:
The patent enables data to skip through the network in a streamlined manner by using direct routing paths through the M stages. The circular shift capability and efficient switching elements allow data to move rapidly through the network without unnecessary stops or complex routing detours, thereby reducing overall processing time while maintaining high throughput.
3Device complexity
If minimum-size belief propagation network is implemented, then hardware requirements are reduced, but routing efficiency may worsen
Solution Approach 1:
The patent changes the parameters of the switching elements to achieve minimum size while maintaining efficiency. By optimizing the number of input/output pins and the configuration of stages, the network achieves compact hardware implementation. The routing commands are optimized to work efficiently with these minimum-size elements, ensuring that routing efficiency is not compromised despite the reduced hardware footprint.
Data Source
AI summary
The invention relates to an interconnection network for forward error correction encoders and decoders, including N input terminals, N output terminals, and M stages. Each stage includes switching elements having input pins and output pins. The input pins of the switching elements of the first stage are connected to the input terminals, and the output pins of the switching elements of the last stage are connected to the output terminals. The input and output pins of the switching elements of immediately successive stages are connected in a hardwired fashion so as to form a plurality of interconnection sub-networks for routing respective input values from respective output pins of the switching elements of the first stage to respective input pins of the switching elements of the last stage.