Source/Drain Contact Height Below Gate Stack to Reduce Capacitance
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Solution Overview
Problem
As semiconductor process technology scales down, process variations become more challenging in the manufacturing of integrated circuits, particularly in forming conductive features like gate vias and source/drain contacts, leading to complexity and inefficiencies in integrated circuit fabrication.
Innovation Solution
The implementation of specific guidelines for arranging local interconnects and gate vias in semiconductor structures, including the use of spacers and contact protection layers, to ensure precise alignment and electrical connectivity between source/drain contacts and gate structures, while maintaining efficient use of space and minimizing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If source/drain contacts are formed at conventional heights, then electrical connectivity is achieved, but manufacturing precision deteriorates due to process variations in scaled-down fabrication
Solution Approach 1:
The patent forms source/drain contacts before forming the gate structure, establishing a predetermined height relationship where contacts extend below the gate stack. This preliminary positioning ensures precise alignment with active regions while simplifying subsequent gate formation processes, directly addressing manufacturing precision challenges in scaled-down devices
Solution Approach 2:
The patent introduces vertical dimensionality by extending source/drain contacts below the gate stack height, creating a three-dimensional configuration where contacts have both lateral alignment with active regions and vertical positioning relative to the gate. This dimensional approach enables precise electrical connectivity while maintaining fabrication simplicity
2Reliability
If source/drain contacts are positioned to optimize electrical connectivity, then device performance improves, but capacitance increases due to closer proximity between contacts and gate structures
Solution Approach 1:
The patent segments the source/drain contact structure into distinct portions: a first portion extending below the gate stack for optimal electrical connectivity with active regions, and a second portion that terminates before reaching gate height to minimize capacitive coupling. This segmentation enables simultaneous optimization of connectivity and capacitance reduction
3Ease of manufacture
If conventional layout arrangements are used, then manufacturing process is simpler, but manufacturing precision deteriorates due to increased process variations in scaled-down fabrication
Solution Approach 1:
The patent establishes source/drain contact positions in advance, before gate structure formation, using the contact structures themselves as alignment references for subsequent processing steps. This preliminary action creates a self-aligned fabrication sequence that maintains precision while simplifying the overall manufacturing process
Solution Approach 2:
The source/drain contact structures serve a dual function: they provide electrical connectivity and simultaneously act as alignment guides for forming the gate structure and other features. This self-service approach eliminates the need for separate alignment marks or complex positioning systems, maintaining ease of manufacture while ensuring high precision
Data Source
AI summary
A semiconductor structure is provided and includes a first gate structure, a second gate structure, and at least one local interconnect that extend continuously across a non-active region from a first active region to a second active region. The semiconductor structure further includes a first separation spacer disposed on the first gate structure and first vias on the first gate structure. The first vias are arranged on opposite sides of the first separation spacer are isolated from each other and apart from the first separation spacer by different distances.