Bent Channel Semiconductor Structure for Region-Specific MOSFET Drive

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Solution Overview

Problem

As semiconductor devices are scaled down, the operating characteristics of MOSFETs deteriorate due to increased integration, requiring new methods to improve performance and reliability while addressing structural variations between peripheral and logic cell regions.

Innovation Solution

The semiconductor device incorporates a substrate with distinct regions, featuring active patterns with semiconductor patterns stacked on the substrate, where the channel patterns in the peripheral region are longer and bent, differing from those in the logic cell region, with gate electrodes and dielectric layers optimized for each region to enhance transistor performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If MOSFET sizes are scaled down to increase integration, then device density improves, but operating characteristics deteriorate

Engineering Contradiction:
Improvedevice integration densityVSAvoidMOSFET operating characteristics
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies local quality by creating different channel pattern configurations for different regions. The first channel pattern has a bent shape with first and second bends, while the second channel pattern has a straight shape. This allows peripheral region transistors to have enhanced driving force through bent channels, compensating for the overall size reduction and maintaining reliable operation despite increased integration density.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the geometric parameter of the channel pattern from straight to bent, specifically introducing first and second bends in the first channel pattern. This parameter change increases the channel length and driving force for peripheral region transistors, thereby improving operating characteristics without increasing the overall device footprint, resolving the contradiction between integration density and performance.

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If uniform transistor design is used across all regions, then manufacturing simplicity is maintained, but performance optimization for different regions is lost

Engineering Contradiction:
Improvetransistor design uniformityVSAvoidregion-specific transistor performance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent implements local quality by designing region-specific channel patterns. The first channel pattern for peripheral region transistors includes bends to increase driving force, while the second channel pattern for logic cell region transistors remains straight. This localized differentiation optimizes performance for each region's specific requirements while maintaining a systematic manufacturing approach.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the substrate into distinct regions (first region and second region) with different transistor design requirements. The first region receives bent channel patterns for high driving force, while the second region receives straight channel patterns for standard performance. This segmentation allows performance optimization without complicating the overall manufacturing process.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11901357B2Semiconductor device
Publication Date: 2024.02.13 SAMSUNG ELECTRONICS CO LTD
  • US11901357B2 patent drawing
  • US11901357B2 patent drawing
  • US11901357B2 patent drawing

AI summary

A semiconductor device including a substrate that includes first and second regions; a first active pattern on the first region, the first active pattern including first source/drain patterns and a first channel pattern between the first source/drain patterns; a second active pattern on the second region, the second active pattern including second source/drain patterns and a second channel pattern between the second source/drain patterns; and a first gate electrode on the first channel pattern and a second gate electrode on the second channel pattern, wherein a length of the first channel pattern is greater than a length of the second channel pattern, each of the first channel pattern and the second channel pattern includes a plurality of semiconductor patterns stacked on the substrate, and at least two semiconductor patterns of the first channel pattern are bent away from or toward a bottom surface of the substrate.