Bent Conductive Lines for Semiconductor Integration Density

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Solution Overview

Problem

The limitations of photo lithography in reducing line and space widths of patterns in semiconductor devices hinder the formation of fine patterns and efficient alignment of metal wires and contact pads in narrow areas, necessitating alternative technologies for higher integration.

Innovation Solution

A semiconductor device design featuring bent conductive lines grouped into multiple sections with varying lengths and orientations, allowing for efficient arrangement of conductive lines and contact pads without wasted space, utilizing a method that includes forming mask patterns and etching processes to create these patterns as etch barriers, thereby minimizing interference between adjacent memory blocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If photo lithography is used to form patterns, then the manufacturing process is simple and well-established, but the line width and space width cannot be reduced below the intrinsic resolution limit

Engineering Contradiction:
Improveline width and space widthVSAvoidintrinsic resolution limit
Core Design Contradiction:
Manufacturing precisionVSMeasurement precision

Solution Approach 1:

The conductive lines are divided into multiple groups with different first region lengths, creating segmented patterns that allow finer effective pitch than the lithography resolution limit. This segmentation enables the formation of fine patterns by using the spacer thickness (determined by ALD process) rather than lithography resolution as the limiting factor.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A spacer layer is introduced as an intermediary element between the mandrel pattern and the final conductive pattern. The spacer acts as a mediator that transfers the pattern from the lithography-defined mandrel to the final conductive structure, enabling sub-lithography resolution features through conformal deposition and anisotropic etching.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If more conductive lines and contact pads are arranged in a narrow area, then integration density improves, but interference between adjacent memory blocks increases

Engineering Contradiction:
Improveintegration densityVSAvoidinterference between adjacent memory blocks
Core Design Contradiction:
Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

The conductive lines in different groups have asymmetric first region lengths, with the first group having a longer first region than the second group. This asymmetric design creates staggered second regions that are spaced apart, reducing interference between adjacent memory blocks while maintaining high integration density.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The conductive lines are arranged in multiple groups along the first direction with varying first region lengths, creating a two-dimensional staggered pattern. This dimensional arrangement allows contact pads to be positioned in spaces between conductive lines, efficiently utilizing the narrow area while minimizing interference through spatial separation.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If conductive lines are arranged in parallel with uniform length, then manufacturing is simple, but wasted space requires dummy lines to be formed

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidwasted space
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

The conductive lines are segmented into groups with different first region lengths, eliminating the need for uniform length and dummy lines. This segmentation allows the second regions to be positioned at different locations along the first direction, filling previously wasted spaces and improving area utilization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different groups of conductive lines have different first region lengths tailored to their specific positions and functions. This local quality variation optimizes the layout by placing contact pads in spaces between conductive lines where they would otherwise be wasted, eliminating the need for dummy lines while maintaining manufacturing feasibility.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS8766452B2Semiconductor device including conductive lines and pads
Publication Date: 2014.07.01 SK HYNIX INC
  • US8766452B2 patent drawing
  • US8766452B2 patent drawing
  • US8766452B2 patent drawing

AI summary

A semiconductor device having a conductive pattern includes a plurality of conductive lines extending in parallel, each having a first region extending in a first direction and a second region coupled to the first region and extending in a second direction crossing the first direction, and a plurality of contact pads, each coupled to a respective conductive line of the second regions, wherein the conductive lines are grouped and arranged in a plurality of groups, the first region of a first group is longer than the first region of a second group, and the second region of the first group and the second region of the second group are spaced apart from each other.