Bent Element Regions in Semiconductor Memory Devices
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Solution Overview
Problem
In NAND flash memory devices, the miniaturization of cell units leads to increased contact resistance due to reduced contact area and positional displacement issues, making it difficult to connect element regions and contact plugs effectively.
Innovation Solution
The semiconductor memory device incorporates bent portions in element regions with wider areas to facilitate contact plug connection, maintaining a stable contact area and reducing contact resistance by arranging select transistors and word lines in a specific geometric configuration, ensuring proper alignment and spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the minimum processing size F is reduced to increase memory capacity, then the memory capacity increases, but the contact area between element region and contact plug decreases and positional displacement increases
Solution Approach 1:
The patent introduces a bent portion that extends in a direction different from the main element region, effectively utilizing spatial arrangement in multiple dimensions. The bent portion protrudes in a direction intersecting the element region extension direction, allowing contact plugs to be positioned more accurately despite miniaturization, thereby resolving the alignment precision issue while maintaining high memory capacity.
Solution Approach 2:
The patent applies different structural characteristics to different regions: the main element region maintains minimum processing size F for high density, while the bent portion has a wider width (1.5-3 times F) specifically at the contact area to ensure adequate contact area and alignment tolerance. This local differentiation resolves both the capacity and precision contradictions.
2Quantity of substance
If the element region width is reduced to minimum processing size F to increase capacity, then the memory capacity increases, but the contact resistance increases due to reduced contact area
Solution Approach 1:
The element region is designed with non-uniform width: the main body has width F for high density, while the bent portion has increased width (1.5-3 times F) specifically at the contact area. This local widening ensures adequate contact area and low contact resistance without sacrificing overall memory capacity.
Solution Approach 2:
Instead of uniformly increasing element region width in one direction, the patent extends the contact area in a different direction through the bent portion, which protrudes in a direction intersecting the element region extension direction. This dimensional approach provides adequate contact area while maintaining high memory capacity.
3Reliability
If contact plugs are arranged in a zigzag manner to ensure distance to contact section, then breakdown voltage is ensured, but the element region other than widened portion must be formed larger than minimum processing size F
Solution Approach 1:
The patent uses a bent portion that protrudes in a direction intersecting the element region extension direction, creating a spatial arrangement that ensures adequate distance to contact sections for breakdown voltage requirements, while keeping the main element region at minimum processing size F for high capacity.
Solution Approach 2:
The widened bent portion is localized only where needed for contact connection, while the majority of the element region maintains minimum processing size F. This selective widening ensures breakdown voltage requirements are met without sacrificing overall memory capacity.
Data Source
AI summary
A semiconductor memory device includes first and second element regions having a rectangular bent portion and a pair of straight line portions connected to both ends of the bent portions, respectively. The pair of straight line portions extends in an opposite direction each other along a first direction. A first element region is arranged in parallel with the second element region so that the first and second element regions are isolated by an element isolation region, and the first and second bent portions are arranged along a second direction in which the first direction intersects with the second direction at an acute angle. A select gate line connected to select transistors extends in the second direction. A plurality of word lines connected to the memory cells are arranged in parallel with the select gate line in an opposite side of the bent portions with respect to the select gate line.