Bent Gate Sidewalls Preventing Electrical Shorts
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Solution Overview
Problem
As the semiconductor industry advances to smaller technology nodes, the decreasing pitch and distance between gate structures and adjacent contacts lead to potential electrical short circuits due to reduced space, necessitating a solution to prevent bridge formation and ensure reliable contact placement.
Innovation Solution
The formation of a gate structure with bent sidewalls, achieved through a recessed gate electrode layer and a strained layer with tensile stress, which bends the gate dielectric layer inwards, increasing the distance between the gate structure and adjacent contacts, thereby avoiding electrical short circuits and maintaining the gate filling process window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pitch between gate structures and adjacent contacts is reduced to increase device density, then productivity and device density are improved, but the risk of electrical short circuits and bridge formation increases
Solution Approach 1:
The gate structure employs bent sidewalls with a curvature radius of 5-20 nm instead of straight vertical walls. This curvature causes the top width of the gate structure to be smaller than the bottom width, effectively reducing the lateral extent of the gate at the top level and increasing the clearance to adjacent contacts, thereby preventing bridge formation while maintaining high device density
Solution Approach 2:
The patent modifies the geometric parameters of the gate structure by creating a non-uniform width profile through bent sidewalls. The curvature radius parameter (5-20 nm) is specifically controlled to achieve the desired shrinkage effect, transforming the gate from a rectangular prism to a shape with tapered top edges, which increases spacing to contacts
2Productivity
If the gate structure dimensions are reduced to increase device density, then productivity is improved, but manufacturing precision and process window are worsened
Solution Approach 1:
The gate structure is formed in two distinct stages: first, a dummy gate structure is formed with standard dimensions using conventional lithography and deposition processes; second, the actual gate structure with bent sidewalls is created by removing the dummy gate and depositing new gate materials that conform to the recessed sidewalls. This segmentation allows the first stage to use standard manufacturing processes while the second stage creates the precision bent geometry
Solution Approach 2:
A dummy gate structure is formed in advance with standard dimensions and materials before the actual gate structure is created. This preliminary structure serves as a template and spacer definition, allowing subsequent processes to form the bent sidewalls with precise geometry while maintaining the original gate pattern alignment
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents bridge formation between gate structures and contacts, enhancing the reliability and yield of semiconductor devices by increasing the distance between them, even at advanced technology nodes like 10 nm, 7 nm, 5 nm, and 3 nm, while preserving the gate filling process window.
Implementation Method 1
a strained layer having a tensile stress is formed around the gate structure to apply a stress on a gate dielectric layer for bending the gate dielectric layer inwards and towards the gate electrode layer
Data Source
AI summary
A method of fabricating a semiconductor device includes forming a dummy gate structure on a substrate, forming gate spacers on sidewalls of the dummy gate structure, and depositing an interlayer dielectric layer around the gate spacers. The method also includes removing the dummy gate structure to form a space between the gate spacers, and forming a gate structure in the space, wherein the gate structure includes a gate dielectric layer and a gate electrode layer over the gate dielectric layer. The method further includes removing a portion of the gate electrode layer to form a recess that is surrounded by the gate dielectric layer. In addition, the method includes implanting on the interlayer dielectric layer to form a strained layer for bending the gate dielectric layer and the gate spacers towards the recess.