Bent Polysilicon Gate Structure for RF Switch Layout Optimization
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Solution Overview
Problem
Conventional RF switches require significant layout area due to the large size of series-connected transistors, which increases fabrication costs and reduces integration efficiency in SOI CMOS technology.
Innovation Solution
A bent polysilicon gate structure is introduced in SOI CMOS transistors, with polysilicon gate fingers offset along a central axis, allowing for a compact layout by varying the length of source/drain regions and optimizing contact placement, thereby reducing the required layout area without modifying conventional SOI CMOS process nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional rectangular polysilicon gate fingers are used, then the transistor structure is simple to fabricate, but the layout area is large
Solution Approach 1:
The patent applies curvature by introducing bent connector portions that join rectangular gate finger portions at angles (e.g., 90 degrees) instead of using straight lines. This bending allows the gate structure to fit more efficiently within the active region, reducing the overall layout area while maintaining the rectangular source/drain regions for simple fabrication
Solution Approach 2:
The patent utilizes the two-dimensional layout space more effectively by arranging gate fingers in a bent pattern rather than a straight linear arrangement. The connector portions extend in directions perpendicular to the main gate finger portions, allowing better space utilization and reduced layout area without increasing structural complexity significantly
2Productivity
If series-connected transistors are made large to ensure proper operation, then device performance is maintained, but fabrication cost increases due to larger die area
Solution Approach 1:
The bent gate structure allows transistors to be packed more densely on the die, enabling more transistors to be fabricated in series without increasing the overall die area. This improves integration efficiency and reduces fabrication costs while maintaining proper transistor operation
Solution Approach 2:
The patent merges multiple gate finger portions and connector portions into a single integrated bent gate structure that controls a single active region. This consolidation allows for more efficient use of die area while maintaining the series-connected transistor configuration needed for RF switch operation
Data Source
AI summary
A semiconductor structure includes a plurality of source/drain regions, a plurality of channel/body regions located between the source/drain regions, and a polysilicon gate structure located over the plurality of channel/body regions. The polysilicon gate structure includes a plurality of polysilicon gate fingers, each extending over a corresponding one of the channel/body regions. Each polysilicon gate finger includes first and second rectangular portions that extend in parallel with a first axis, and a connector portion that introduces an offset between the first and second rectangular portions along the first axis. This offset results in each source/drain region having a first section with a first length, and a second section with a second length, greater than the first length. A single column of contacts are provided in the first section of each source/drain region, and multiple columns of contacts are provided in the second section of each source/drain region.