Bent Polysilicon Gate Structure for Compact RF Switch Layout
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Solution Overview
Problem
Conventional RF switches require significant layout area due to the large size of series-connected transistors, which increases the size of RF switch devices and affects their integration into smaller form factors.
Innovation Solution
A bent polysilicon gate structure for SOI CMOS transistors is introduced, where each polysilicon gate finger has a central offset, allowing for a compact layout by varying the length and width of source/drain regions and adjusting the pitch between contacts, thereby reducing the overall layout area without modifying conventional SOI CMOS process nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional RF switches use series-connected transistors with standard layout, then the transistors can provide required voltage handling and isolation, but the layout area becomes excessively large
Solution Approach 1:
The patent transforms the conventional linear arrangement of transistors into a two-dimensional folded layout by introducing intermediate connection structures. This allows transistors to be arranged in a compact folded pattern rather than extending linearly, significantly reducing the layout area while maintaining the series connection topology required for voltage handling and isolation.
Solution Approach 2:
The patent implements nesting by placing intermediate connection structures within or adjacent to the transistor regions. The intermediate connections are integrated into the existing transistor layout rather than occupying separate external space, allowing the circuit to fold back on itself and reduce the overall footprint while maintaining electrical connectivity.
2Area of stationary object
If the layout area is reduced by compacting transistor arrangement, then integration into smaller form factors is enabled, but the on-resistance and capacitance may increase
Solution Approach 1:
The patent introduces intermediate connection structures that act as mediators between series-connected transistors. These intermediate connections provide low-resistance pathways that compensate for the increased path length introduced by the folded layout, thereby maintaining low on-resistance. The intermediate structures also serve as capacitance management points, allowing for optimized electrical characteristics despite the compact arrangement.
3Ease of manufacture
If standard SOI CMOS process nodes are used, then fabrication cost and integration are minimized, but the transistor size required for RF switch operation results in large overall device footprint
Solution Approach 1:
The patent maintains compatibility with standard SOI CMOS process nodes while achieving compact integration by transitioning from a one-dimensional linear transistor arrangement to a two-dimensional folded layout. This dimensional transformation allows the use of conventional fabrication processes without modification while dramatically reducing the device footprint through optimized spatial arrangement of transistors and intermediate connections.
Data Source
AI summary
A structure includes channel regions located between source/drain regions, and a polysilicon gate structure including a plurality of gate fingers, each extending over a corresponding channel region. Each gate finger includes first and second rectangular portions extending in parallel with a first axis, and a connector portion that introduces an offset between the first and second rectangular portions along a second axis. This offset causes each source/drain region to have a first section with a first length along the second axis, and a second section with a second length along the second axis, greater than the first length. A single column of contacts having a first width along the second axis is provided in the first section of each source/drain region, and a single column of contacts having a second width along the second axis, greater than the first width, is provided in the second section of each source/drain region.