Display Device Bent Scan-Line Layout for Compact Capacitors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing display devices experience luminance deviation and require a significant area for capacitors, hindering high resolution performance.
Innovation Solution
The display device design includes a substrate with specific transistor configurations and capacitors, featuring a second scan line with unique directional bends and overlapping structures to minimize capacitor area and reduce luminance deviation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional capacitor layout is used in display devices, then the capacitor can store necessary charge, but the capacitor occupies a large area which hinders high resolution performance
Solution Approach 1:
The scan line is designed with bent portions instead of straight lines. Specifically, the scan line includes a first portion extending in a first direction, a second portion bent from the first portion and extending in a second direction, and a third portion bent from the second portion and extending in the first direction. This curved layout reduces the area occupied by the capacitor while maintaining its functionality.
Solution Approach 2:
The scan line transitions from a two-dimensional straight path to a three-dimensional curved path by bending in multiple directions. The scan line extends in the first direction, then bends to extend in the second direction, and finally bends again to extend in the first direction, utilizing spatial dimensionality to reduce area occupation.
2Reliability
If the scan line is extended to cover necessary transistor regions, then transistor control is improved, but the scan line overlaps with connection electrodes causing parasitic capacitance and luminance deviation
Solution Approach 1:
The harmful overlap between the scan line and connection electrode is extracted and eliminated. The scan line is specifically routed to overlap with the semiconductor layer while being separated from the connection electrode in plan view, removing the parasitic capacitance source while maintaining necessary transistor control.
Solution Approach 2:
The scan line has different spatial relationships with different components: it overlaps with the semiconductor layer in certain regions to control transistors, but is separated from the connection electrode in plan view to avoid parasitic capacitance. This localized differentiation of spatial quality resolves the contradiction.
Data Source
AI summary
A display device comprises a substrate, a first channel above the substrate, a first gate electrode overlapping the first channel, a storage electrode above the first gate electrode, a first connection electrode above the storage electrode, and connected with the first gate electrode, a third channel of a third transistor above the substrate, and a second scan line including a third gate electrode overlapping the third channel, wherein the third transistor includes a second electrode connected with the first connection electrode, and wherein the second scan line includes a first portion including the third gate electrode, and extending in a first direction, a second portion bent from the first portion, and extending in a second direction in parallel with a first side of the storage electrode, and a third portion bent from the second portion, and extending in the first direction in parallel with a second side of the storage electrode.