Bent Scan-Line Pixel Layout for Lower Luminance Deviation
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Solution Overview
Problem
Existing display devices experience luminance deviation and require a significant area for capacitors, hindering high resolution.
Innovation Solution
The display device design includes a substrate with specific transistor configurations and capacitor arrangements, utilizing a second scan line with bent portions to minimize overlap with connection electrodes and storage electrodes, reducing capacitor area and luminance deviation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional capacitor arrangements are used in display devices, then the capacitor can store necessary charge, but the capacitor occupies significant area which hinders high resolution
Solution Approach 1:
The storage electrode is merged with the gate electrode of the third transistor, forming a shared structure. This integration allows the capacitor to occupy less area while maintaining its charge storage function, thereby enabling higher resolution display devices
Solution Approach 2:
The gate electrode of the third transistor serves dual purposes: as the gate electrode for transistor operation and as the storage electrode for the capacitor. This multi-functionality reduces the total number of separate components and minimizes the area required for capacitor implementation
2Reliability
If conventional scan line routing is used, then the scan line can connect transistors, but overlap with connection electrodes causes luminance deviation
Solution Approach 1:
The second scan line is configured with bent portions instead of straight lines. These curved sections allow the scan line to route around connection electrodes, minimizing overlap and reducing parasitic capacitance that would cause luminance deviation, while still maintaining electrical connectivity
Data Source
AI summary
A display device comprises a substrate, a first channel above the substrate, a first gate electrode overlapping the first channel, a storage electrode above the first gate electrode, a first connection electrode above the storage electrode, and connected with the first gate electrode, a third channel of a third transistor above the substrate, and a second scan line including a third gate electrode overlapping the third channel, wherein the third transistor includes a second electrode connected with the first connection electrode, and wherein the second scan line includes a first portion including the third gate electrode, and extending in a first direction, a second portion bent from the first portion, and extending in a second direction in parallel with a first side of the storage electrode, and a third portion bent from the second portion, and extending in the first direction in parallel with a second side of the storage electrode.