BEOL 2D Transistor Etching for High-Density Memory Cells
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in creating high-density transistors for memory storage due to limitations in etching processes, particularly with 2D layers that are only 1 nanometer thick, which makes precise etching difficult and damages the layers during dry etching processes.
Innovation Solution
The implementation of a combination of dry and wet etch processes to create cavities in the dielectric and cap layers, allowing for precise stopping on the 2D layer without damaging it, enabling the formation of sources and drains that electrically couple with the 2D layer, and using a MFMIS structure with a ferroelectric layer for enhanced memory storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dry etching process is used to create cavities in dielectric and cap layers, then etching precision is improved, but the 2D layer is damaged due to its thinness (1 nanometer)
Solution Approach 1:
The etching process is segmented into two distinct stages: first a dry etch process creates initial cavities in the dielectric layer with high precision, then a wet etch process completes the cavity formation through the cap layer. This segmentation allows each process to be optimized for its specific function - dry etching for precision and wet etching for gentle completion without damaging the thin 2D layer.
Solution Approach 2:
The cap layer serves as an intermediary protective element between the dielectric layer and the 2D layer. By etching through the cap layer using wet etching after initial cavity formation, the 2D layer is protected from direct exposure to aggressive dry etching conditions while still achieving precise cavity formation.
2Productivity
If 2D layer thickness is reduced to 1 nanometer for high-density transistors, then transistor density is improved, but etching difficulty increases and layer damage occurs
Solution Approach 1:
The manufacturing process is segmented into controlled stages where the cap layer is etched separately from the dielectric layer. This allows the thin 2D layer to be protected during the most challenging etching steps while still achieving the high density required for advanced transistors.
Solution Approach 2:
The cap layer acts as a sacrificial intermediary that protects the ultra-thin 2D layer during manufacturing. By removing the cap layer through wet etching after cavity formation, the 2D layer remains intact despite its minimal thickness, enabling high-density transistor fabrication.
3Device complexity
If conventional etching processes are used, then process simplicity is maintained, but precise stopping on 2D layer without damage is not achieved
Solution Approach 1:
The etching process is divided into two sequential steps: dry etching for initial cavity formation with precise depth control, and wet etching for completing the cavity through the cap layer. This segmentation achieves manufacturing precision that cannot be obtained with a single conventional etching process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of high-density memory cells with precise etching of 2D layers, improving the integration of 2D transistors in memory devices and enhancing memory storage capabilities while maintaining the integrity of the 2D layers.
Implementation Method 1
forming a second cavity in the cap layer that extends to a surface of the 2D layer by performing a wet etch
Implementation Method 2
forming a first cavity in the dielectric layer that extends to a surface of the cap layer by performing a dry etch
Implementation Method 3
using a MFMIS structure with a ferroelectric layer for enhanced memory storage
Data Source
AI summary
Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques directed to creating back end of line 2D transistors that may be used as access transistors for a memory cell. In embodiments, a combination wet etch and dry etch process may be used to form the 2D transistors. Other embodiments may be described and/or claimed.