BEOL Air-Gap Structure for Small-Pitch Parasitic Capacitance

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Solution Overview

Problem

In small pitch patterns, the parasitic capacitance effect is significant due to the close proximity of metal lines, leading to increased propagation delay and noise, which compromises electrical performance and reliability.

Innovation Solution

The introduction of a closed air gap in the dielectric layer between conductive portions, formed by recessing the dielectric layer and sealing it with a spacer, reduces parasitic capacitance and enhances electrical isolation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If metal lines are placed close together to achieve small pitch patterns, then device integration density is improved, but parasitic capacitance increases leading to degraded electrical performance

Engineering Contradiction:
Improveintegration densityVSAvoidparasitic capacitance
Core Design Contradiction:
Area of moving objectVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an air gap as an intermediary structure between adjacent metal lines in the BEOL. This air gap, formed by recessing the dielectric layer and filling with air (or low-k material), acts as a mediator that reduces the parasitic capacitance coupling between closely spaced metal lines while maintaining the high integration density required for small pitch patterns

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the dielectric parameter between metal lines from a conventional solid dielectric material to an air gap (or low-k material). This parameter change in the dielectric constant (k-value) directly reduces the parasitic capacitance between adjacent conductors, allowing small pitch patterns to maintain good electrical performance

Inventive Principle:
Principle #35Parameter changes

2Object-affected harmful factors

If dielectric layer is recessed to form air gap, then parasitic capacitance is reduced, but manufacturing process complexity increases

Engineering Contradiction:
Improveparasitic capacitanceVSAvoidmanufacturing process complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent performs preliminary actions by forming the recess in the dielectric layer before depositing the air gap filling material. The recess is created using selective etching processes that prepare the structure in advance, allowing subsequent simple deposition or removal steps to complete the air gap formation without requiring complex in-situ processing

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts material from the dielectric layer to create the recess that will become the air gap. By removing a portion of the dielectric material selectively between metal lines, the structure is simplified to contain air (or vacuum) in that region, reducing parasitic capacitance while using standard etching and deposition techniques

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20250133800A1Semiconductor device and manufacturing method thereof
Publication Date: 2025.04.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250133800A1 patent drawing
  • US20250133800A1 patent drawing
  • US20250133800A1 patent drawing

AI summary

A semiconductor device includes a MEOL structure and a BEOL structure. The BEOL structure is formed over the MEOL structure and includes a first dielectric layer, a spacer and a conductive portion. The first dielectric layer has a lateral surface and a recess, wherein the recess is recessed with respect to the lateral surface. The spacer is formed the lateral surface and covers an opening of the recess. The conductive portion is formed adjacent to the spacer.