BEOL Interconnects with Columnar Air Gaps and High-k Dielectrics
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in integrating high-k and low-k dielectric materials for back-end-of-line (BEOL) metalization structures due to difficulties in polishing low mechanical strength porous dielectrics and achieving reasonable coverage with conventional deposition technologies, which affects capacitance and mechanical properties.
Innovation Solution
A method involving a two-phase photoresist material for creating columnar air gaps using reactive ion etching (RIE) and selective cap formation to form interconnect structures with either air gaps or high-k materials embedded within the dielectric, allowing for simultaneous integration of high-k and low-k dielectrics without requiring new materials or module development.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If porous low-k dielectric materials are used to reduce capacitance, then dielectric constant is reduced, but mechanical strength deteriorates
Solution Approach 1:
The patent applies local quality by creating regions with different dielectric constants within the same inter-level dielectric layer. Air gaps (k≈1.0) are formed in specific locations where capacitance reduction is needed, while other regions maintain higher mechanical strength. This allows the structure to have low average dielectric constant without compromising overall mechanical integrity, as the porous/air regions are localized rather than universal.
2Shape
If conventional CMP polishing is used, then flat surface is achieved, but polishing of porous dielectric is difficult
Solution Approach 1:
The patent segments the inter-level dielectric layer into regions with different mechanical properties. By forming air gaps or porous regions in specific locations rather than uniformly throughout, the structure can be polished more effectively. The non-porous regions provide structural support during CMP processing, while the porous/air regions are confined to areas where they are needed for capacitance reduction, making the overall polishing process more manageable.
3Quantity of substance
If conventional PVD deposition is used, then barrier layer is deposited, but coverage on porous dielectric surface is insufficient
Solution Approach 1:
The patent applies local quality by concentrating barrier layer deposition in regions where porous dielectric is present. The metallic cap formation and barrier layer deposition are performed selectively in areas containing air gaps or porous structures, ensuring adequate coverage where it is most needed. This targeted approach improves deposition effectiveness without requiring complete re-deposition across the entire wafer surface.
4Adaptability or versatility
If multiple separate processes are used for high-k and low-k integration, then both dielectric types can be formed, but process complexity increases
Solution Approach 1:
The patent merges the formation of high-k and low-k dielectric regions into a single integrated process flow. By using selective cap formation and a unified pattern transfer process that can create both air gap regions and high-k filled regions simultaneously, the patent reduces process complexity. The same photoresist patterning and etching steps that create air gaps can also define regions for high-k material deposition, eliminating the need for separate critical masking and processing steps for each dielectric type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances capacitance modification by allowing for both high-k and low-k interconnects within existing BEOL processes, improving mechanical properties and reducing costs by maintaining compatibility with current processes and avoiding the need for additional masking or exotic materials.
Implementation Method 1
The two-phase separated photoresist material pattern is transferred to the first ILD layer to create the columnar air gap structure
Implementation Method 2
subsequent reactive ion etching (RIE) processing
Data Source
AI summary
A method for fabricating and back-end-of-line (BEOL) metalization structures includes simultaneous high-k and low-k dielectric regions. An interconnect structure includes a first inter-level dielectric (ILD) layer and a second ILD layer with the first ILD layer underlying the second ILD layer. A plurality of columnar air gaps is formed in the first ILD. The columnar air gap structure is created using a two-phase photoresist material for providing different etching selectivity during subsequent processing.